2000 Oct 24

13

Philips Semiconductors

Product specification

noise frequency synthesizer

TSA5060A

Notes

1. Asymmetrical drive on pin RFA or RFB; see Fig.3.

2. The drive level is expected with the crystal at series resonance with a series resistance of 50

Ω. The value will be

different with another crystal.

3. To drive pin XTAL from the pin XT/COMP of another TSA5060A, couple the signal through a capacitor of 1 nF

(to remove the DC level) in series with an 1.2 k

Ω resistor; see Fig.5.

specification. The worst situation is a bus voltage of 5 V + 10%. In this case the noise margin is 0.55 V below

0.3

× 5.5 V, thus 1.1 V.

specification. The worst situation is a bus voltage of 3.3 V

− 10%. In this case the noise margin is 0.59 V above

0.7

× 2.97 V, thus 2.67 V.

XT/COMP output (pin XT/COMP)

AC output voltage (peak-to-peak value)

XCE = 1

−

400

−

mV

Input/output and output ports (pins P0, P1, P2 and P3)

port leakage current

−−

10

µA

output port saturation voltage

−

0.2

0.4

V

LOW-level input voltage

−−

1.5

V

HIGH-level input voltage

3.0

−−

V

ADC input (pin ADC)

HIGH-level input leakage current

−−

10

µA

LOW-level input leakage current

−10

−−

µA

Address selection (pin AS)

HIGH-level input leakage current

−−

1mA

LOW-level input leakage current

−0.5

−−

mA

SCL and SDA inputs (pins SCL and SDA)

LOW-level input voltage

including noise margin;

note 4

−−

1.1

V

HIGH-level input voltage

including noise margin;

note 5

2.67

−−

V

HIGH-level input leakage current

−−

10

µA

−−

10

µA

LOW-level input leakage current

−10

−−

µA

SCL clock frequency

−−

400

kHz

SDA output (pin SDA)

output voltage during acknowledge

−−

0.4

V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT