12F615 datasheet(109/168 Pages) MICROCHIP

109 / 168 page

Preliminary

DS41302A-page 107

PIC12F609/615/12HV609/615

11.6.2

WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst-

case conditions (i.e., VDD = Min., Temperature = Max.,

Max. WDT prescaler) it may take several seconds

before a WDT time out occurs.

FIGURE 11-2:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 11-9:

SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

TABLE 11-8:

WDT STATUS

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

OPTION_REG

GPPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

CONFIG

IOSCFS

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

—

Legend:

Shaded cells are not used by the Watchdog Timer.

Note

See Register 11-1 for operation of all Configuration Word register bits.

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-Out

PS<2:0>

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note

T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

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