8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including

the following guidelines:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole or through the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance

power sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

– The TLVx365-Q1 is capable of peak output current (in excess of 50 mA). Applications with low impedance

loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger

bypass capacitors, such as 1-µF solid tantalum capacitors, can improve dynamic performance in these

applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed

to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Figure 8-8 shows that keeping RF and RG

close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

8.4.2 Layout Example

OUT A

-IN A

+IN A

V–

OUT B

-IN B

+IN B

V+

VS–

GND

Ground (GND) plane on another layer

Keep input traces short

and run the input traces

as far away from

the supply lines

as possible.

Place components

close to device and to

each other to reduce

parasitic errors.

Use low-ESR,

ceramic bypass

capacitor. Place as

close to the device

as possible.

VIN A

GND

RF

RG

VIN B

GND

RF

RG

VS+

GND

VOUT A

VOUT B

(Schematic Representation)

+

VIN B

VOUT B

RG

RF

+

VIN A

VOUT A

RG

RF

Use low-ESR,

ceramic bypass

capacitor. Place as

close to the device

as possible.

Figure 8-8. Layout Recommendation for TLV2365-Q1 SOIC Package

TLV365-Q1, TLV2365-Q1

SBOSAB8B – JUNE 2023 – REVISED SEPTEMBER 2024

www.ti.com

18

Submit Document Feedback

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TLV365-Q1 TLV2365-Q1