S2043 datasheet(3/20 Pages) AMCC

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Applied Micro Circuits Corporation

6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

S2042/S2043

Reference Clock Input

The reference clock input (REFCLK) must be sup-

plied with a single-ended AC coupled crystal clock

source with 100 PPM tolerance to assure that the

transmitted data meets the Fibre Channel frequency

limits. The internal serial clock is frequency locked to

the reference clock. The word rate clock (TCLK, TCLKN)

output frequency is determined by the selected oper-

ating speed and word width. Refer to Table 1 for

TCLK/TCLKN clock frequencies.

Table 1. Transmitter Operating Modes

Data Rate

(Mbits/sec)

RATESEL

REFSEL

DWS

Word

Width

(Bits)

Reference

Clock

Frequency

(MHz)

1062.5

531.25

265.625

Open

TCLK/TCLKN

Frequency

(MHz)

53.125

26.5625

106.25

53.125

26.5625

Parallel/Serial Conversion

The parallel-to-serial converter takes in 10-bit or 20-

bit wide data from the input latch and converts it to a

serial data stream. Parallel data is latched into the

transmitter on the positive going edge of REFCLK.

The data is then clocked synchronous to the clock

synthesis unit serial clock into the serial output shift

generated bit clock which is 10 times the REFCLK

input frequency. The state of the serial outputs is

controlled by the output enable pins, OE0 and OE1.

D10 is transmitted first in 10-bit mode. D0 is trans-

mitted first in 20-bit mode. Table 2 shows the mapping

of the parallel data to the 8B/10B codes.

10-Bit/20-Bit Mode

The S2042 operates with either 10-bit or 20-bit par-

allel data inputs. Word width is selectable via the

DWS pin. In 10-bit mode, D10–D19 are used and

D0–D9 are ignored.

First Data Byte

Second Data Byte

TX[00:19] or

RX[00:19]

8b/10b alphabetic

representation

First bit transmitted in 20-bit mode

First bit transmitted in 10-bit mode

Table 2. Data Mapping to 8b/10b Alphabetic Representation

Figure 4. S2043 Functional Block Diagram

PLL CLOCK

RECOVERY

2:1

BITCLK

SYNC

DETECT

LOGIC

CONTROL

LOGIC

REFCLK

REFSEL

RATESEL

LOCK_REF

RLX

RLY

LPEN

DWS

SYNCEN

LOCKDETN

D(0..19)

RCLK

SYNC

RCLKN

SHIFT

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