S2043 datasheet(4/20 Pages) AMCC

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Applied Micro Circuits Corporation

6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

S2042/S2043

S2043 RECEIVER FUNCTIONAL

DESCRIPTION

The S2043 receiver is designed to implement the

ANSI X3T11 Fibre Channel specification receiver

functions. A block diagram showing the basic chip

function is provided in Figure 4.

Whenever a signal is present, the S2043 attempts to

achieve synchronization on both bit and transmis-

sion-word boundaries of the received encoded bit

stream. Received data from the incoming bit stream

is provided on the device’s parallel data outputs.

The S2043 accepts serial encoded data from a fiber

optic or coaxial cable interface. The serial input stream

is the result of the serialization of 8B/10B encoded

data by an FC compatible transmitter. Clock recov-

ery is performed on-chip, with the output data

presented to the Fibre Channel transmission layer

as 10- or 20-bit parallel data. The chip is program-

mable to operate at the Fibre Channel specified

operating frequencies of 1062, 531 and 266 Mbit/s.

Serial/Parallel Conversion

Serial data is received on the RX, RY pins. The PLL

clock recovery circuit will lock to the data stream if the

clock to be recovered is within

±100 PPM of the inter-

nally generated bit rate clock. The recovered clock is

used to retime the input data stream. The data is

then clocked into the serial to parallel output regis-

ters on the low going edge of RCLK. In 1062 Mbit/

sec, 10-bit mode, data is clocked out on the falling

edge of RCLK and RCLKN.The parallel data out can

be either 10 or 20 bits wide determined by the state

of the DWS pin. The word clock (RCLK) is synchro-

nized to the incoming data stream word boundary by

the detection of the fiber channel K28.5 synchroniza-

tion pattern (0011111010, positive running disparity).

10-Bit/20-Bit Mode

The S2043 will operate with either 10-bit or 20-bit

parallel data outputs. This option is selectable via

the DWS pin. See Table 4. In 10-bit mode, D10-D19

are used and D0-D9 are driven to the logic high state.

Reference Clock Input

The reference clock input must be supplied with a single-

ended AC coupled crystal clock source at

±100 PPM

tolerance. See Table 4 for reference clock frequencies.

Framing

The S2043 provides SYNC character recognition and

data word alignment of the TTL level compatible output

data bus. In systems where the SYNC detect function

is undesired, a LOW on the SYNCEN input disables

the SYNC function and the data will be “un-framed”.

First Data Byte

Second Data Byte

TX[00:19] or

RX[00:19]

8b/10b alphabetic

representation

First bit received in 20-bit mode

First bit received in 10-bit mode

Table 3. Data Mapping to 8b/10b Alphabetic Representation

REFCLK

(Input)

RCLK

(Output)

SYNC

(Output)

PARALLEL

DATA BUS

(Input)

K28.5,

Byte 1

of Data

Byte 2, 3

of Data

Byte 4, 5

of Data

Byte 6, 7

of Data

Byte 8, 9

of Data

Byte 10,

11 of Data

Byte 12,

13 of Data

Byte 14,15

of Data

K28.5

Byte 16

of Data

D10

D11

D12

D13

D14

D15

PARALLEL

DATA BUS

(Output)

SERIAL DATA

K28.5

K28.5,

Byte 1

of Data

Byte 2, 3

of Data

Byte 4, 5

of Data

Byte 6, 7

of Data

Byte 8, 9

of Data

Byte 10,

11 of Data

Byte 12,

13 of Data

Byte 14,15

of Data

K28.5 D16

Figure 5. Functional Waveform

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