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CDB4392 Datasheet(PDF) 35 Page - Cirrus Logic |
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CDB4392 Datasheet(HTML) 35 Page - Cirrus Logic |
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35 / 40 page ![]() CS4392 DS459PP3 35 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Notes: 7. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 8. Data must be held for sufficient time to bridge the transition time of CCLK. 9. For FSCK < 1 MHz Parameter Symbol Min Max Unit SPI Mode CCLK Clock Frequency fsclk -6 MHz RST Rising Edge to CS Falling tsrs 500 - ns CCLK Edge to CS Falling (Note 7) tspi 500 - ns CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 82 - ns CCLK High Time tsch 82 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 8) tdh 15 - ns Rise Time of CCLK and CDIN (Note 9) tr2 -100 ns Fall Time of CCLK and CDIN (Note 9) tf2 -100 ns t r2 t f2 t dsu t dh t sch t scl CS CCL K CD IN t css t csh t spi t srs RST Figure 39. SPI Control Port Timing |
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