ICS853111B datasheet(8/19 Pages) IDT

8 / 19 page

IDT™ / ICS™

1-TO-10, LVPECL/ECL FANOUT BUFFER

ICS853111BY REV. B SEPTEMBER 5, 2007

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

APPLICATION INFORMATION

Figure 2A

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

Single Ended Clock Input

VCC

PCLKx

nPCLKx

0.1u

V_REF

FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT

Figure 2B

shows an example of the differential input that can

be wired to accept single ended LVPECL levels. The reference

voltage level V

BB generated from the device is connected to the

negative input. The C1 capacitor should be located as close as

possible to the input pin.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS

CLK_IN

0.1uF

VDD(or VCC)

VBB

ICS853111B Datasheet(PDF) 8 Page - Integrated Device Technology