CS42428 datasheet(49/73 Pages) CIRRUS

49 / 73 page

DS605F1

CS42428

6.7.4

MASTER CLOCK SOURCE SELECT (SW_CTRLX)

Default = 00

Function:

These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”

on page 56, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0

are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes

unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.

When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes

unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.

6.7.5

FORCE PLL LOCK (FRC_PLL_LK)

Default = 0

Function:

This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on

OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled and the

SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h) (Read Only) register

contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to

properly apply de-emphasis filtering.

6.8

OMCK/PLL_CLK Ratio (address 07h) (Read Only)

6.8.1

OMCK/PLL_CLK RATIO (RATIOX)

Default = xxxxxxxx

Function:

This register allows the user to find the exact absolute frequency of the recovered MCLK coming from

the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For

example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.

SW_CTRL1 SW_CTRL0

UNLOCK

Description

Manual setting, MCLK sourced from PLL.

Manual setting, MCLK sourced from OMCK.

Hold, keep same MCLK source.Auto switch, MCLK

sourced from OMCK.

Auto switch, MCLK sourced from PLL.

Auto switch, MCLK sourced from OMCK.

Table 11. Master Clock Source Select

432

RATIO7(21)RATIO6(20)RATIO5(2-1)RATIO4(2-2)

RATIO3(2-3)RATIO2(2-4)

RATIO1(2-5)RATIO0(2-6)

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