CS42428 datasheet(5/73 Pages) CIRRUS

5 / 73 page

DS605F1

CS42428

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies ............................................................................................ 24

Table 2. Common PLL Output Clock Frequencies..................................................................................... 24

Table 3. Slave Mode Clock Ratios ............................................................................................................. 25

Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26

Table 5. DAC De-Emphasis ....................................................................................................................... 44

Table 6. Digital Interface Formats .............................................................................................................. 45

Table 7. ADC One-Line Mode.................................................................................................................... 45

Table 8. DAC One-Line Mode.................................................................................................................... 45

Table 9. RMCK Divider Settings ................................................................................................................ 48

Table 10. OMCK Frequency Settings ........................................................................................................ 48

Table 11. Master Clock Source Select....................................................................................................... 49

Table 12. PLL Clock Frequency Detection................................................................................................. 50

Table 13. Example Digital Volume Settings ............................................................................................... 53

Table 14. ATAPI Decode ........................................................................................................................... 54

Table 15. Example ADC Input Gain Settings ............................................................................................. 55

Table 16. PLL External Component Values ............................................................................................... 62

CS42428 Datasheet(PDF) 5 Page - Cirrus Logic