DVIULC6-4SC6 datasheet(5/12 Pages) STMICROELECTRONICS

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DVIULC6-4SC6

2 Surge protection application example

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Surge protection application example

If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are

done by two tracks of 10mm long and 0.5 mm large; we assume that the parasitic inductances

Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time

of this spike (tr=1 ns), the voltage VCL has an extra value equal to Lw.dI/dt.

The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns

The over voltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144 V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the

clamping voltage will be:

We can reduce as much as possible these phenomena with simple layout optimization.

It’s the reason why some recommendations have to be followed (see Section 3: How to ensure

a good ESD protection).

Figure 6.

ESD behavior: parasitic phenomena due to unsuitable layout

VCL+ = +39 + 144 = 183 V

VCL- = -34 - 144 = -178 V

VI/O

ESD

SURGE

GND

I/O

+VCC

VBUS

Lw di

V+ =

+V +Lw

BUS

surge >0

surge <0

V- =

-V -Lw

tr=1ns

VCL+

POSITIVE

SURGE

183V

-Lw

tr=1ns

VCL-

NEGATIVE

SURGE

-178V

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