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LPC55S2X Datasheet(PDF) 102 Page - NXP Semiconductors

Part # LPC55S2X
Description  32-bit Arm Cortex®-M33 microcontroller
PDF  132 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S2X Datasheet(HTML) 102 Page - NXP Semiconductors

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NXP Semiconductors
LPC55S2x/LPC552x
32-bit Arm Cortex®-M33 microcontroller
• Ensure that the load capacitors have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the
parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
13.5 Suggested USB full-speed interface solutions
The USB device can be connected to the USB as self-powered device (see Figure 30) or bus-powered device
(see Figure 31).
The USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level. Therefore, if the
USB_VBUS function is connected to the USB connector and the device is self-powered, the USB_VBUS pin
must be protected for situations when
VDD = 0 V.
If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be connected directly to the
VBUS pin on the USB connector.
For such USB applications, the internal pull-down on the GPIO/VBUS pad must be enabled on pins P0_22 or
P1_11 when attaching/de-attaching in the USB application. Enable the internal pull-downs with user software.
For USB ISP mode, the internal resistor pull-down is not enabled on the P0_22 pin where the VBUS pin can be
floating. USB enumeration may still occur when VBUS is not connected.
For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken
to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this
case.
One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The
voltage divider ratio should be such that the USB_VBUS pin is greater than 0.7 VDD to indicate a logic HIGH
while below the 3.6 V allowable maximum voltage.
For the following operating conditions:
VBUSmax = 5.25 V
VDD = 3.6 V
The voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
LPCxxxx
VBAT_DCDC/VBAT_
PMU/VDD/USB_3V3
R1
1.5 κΩ
USB-B
connector
USB_DP
USB_DM
USB_VBUS
VSS
RS = 33 Ω
RS = 33 Ω
USB
USB_CONNECT
R2
R3
D+
D-
Figure 30. USB interface on a self-powered device where USB_VBUS = 5 V
LPC55S2X_LPC552X
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Data sheet
Rev. 2.3 — 29 August 2024
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