Electronic Components Datasheet Search
  English  ▼

X  

STAC9250 Datasheet(PDF) 33 Page - Integrated Device Technology

Part # STAC9250
Description  TWO-CHANNEL HD AUDIO CODEC WITH MODEM & DUAL DIGITAL MICROPHONE INTERFACES
PDF  137 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

STAC9250 Datasheet(HTML) 33 Page - Integrated Device Technology

Back Button STAC9250 Datasheet HTML 29Page - Integrated Device Technology STAC9250 Datasheet HTML 30Page - Integrated Device Technology STAC9250 Datasheet HTML 31Page - Integrated Device Technology STAC9250 Datasheet HTML 32Page - Integrated Device Technology STAC9250 Datasheet HTML 33Page - Integrated Device Technology STAC9250 Datasheet HTML 34Page - Integrated Device Technology STAC9250 Datasheet HTML 35Page - Integrated Device Technology STAC9250 Datasheet HTML 36Page - Integrated Device Technology STAC9250 Datasheet HTML 37Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 33 / 137 page
background image
STAC9250/9251
TWO-CHANNEL HD AUDIO CODEC WITH MODEM & DUAL DIGITAL MICROPHONE INTERFACES
PC AUDIO
IDT™
33
STAC9250/9251
V 1.1 102706
TWO-CHANNEL HD AUDIO CODEC WITH MODEM & DUAL DIGITAL MICROPHONE INTERFACES
5.5.13.
AFG GPIOEn
[1]
Data1
RW
0x0
Data for GPIO1 (Pin 34). If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
[0]
Data0
RW
0x0
Data for GPIO0 (Pin 33). If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
Table 34. AFG GPIOEn Command Verb Format
Verb ID
Payload
Response
Get
F16
00
See bitfield table
Set1
716
See bits [7:0] of bitfield table
0000_0000h
Table 35. AFG GPIOEn Command Response Format
Bit
Bitfield Name
RW
Reset
Description
[31:4]
Rsvd
R
0x0
Reserved
[3]
Mask3
RW
0x0
Enable for GPIO3:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[2]
Mask2
RW
0x0
Enable for GPIO2:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
Table 33. AFG GPIO Command Response Format
Bit
Bitfield Name
RW
Reset
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com