PM7351 datasheet(39/174 Pages) PMC

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RELEASED

PM7351 S/UNI-VORTEX

DATA SHEET

PMC-1980582

ISSUE 5

OCTAL SERIAL LINK MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FUNCTIONAL DESCRIPTION

First, a brief note on terminology. Throughout this document the use of the term

“downstream” implies data read in from the parallel bus (or microprocessor port)

and sent out the LVDS links. However, since the S/UNI-VORTEX is a slave

device and bus direction (transmit or receive) is normally defined with respect to

the bus master, the downstream bus is called the Transmit bus. Conversely,

“upstream” is used to describe the data path from the LVDS to the parallel bus,

which is called the Receive bus.

9.1 Cell Interface

Cell transfer from the S/UNI-VORTEX (bus slave) to a traffic management device

(bus master) in the upstream direction is configurable as either SCI-PHY or Any-

PHY. SCI-PHY is very similar to UTOPIA, but it supports the appended bytes

used by the S/UNI-VORTEX for carrying PHY address information. If the option

to place PHY addressing information in the H5/UDF field is enabled, the SCI-

PHY bus is compatible to a 16 bit Utopia Level 2. Any-PHY defines inband

selection and polling techniques to support a large number of logical channels,

where SCI-PHY is limited to 32 and UTOPIA is limited to 31.

The downstream interface only provides an Any-PHY bus slave interface. While

the downstream cell transfer mechanism is compatible with existing SCI-PHY

devices (or UTOPIA devices supporting extended cells), the channel status

polling is a new extension.

16-bit wide busses plus parity are supported; 8 bit wide is not supported.

9.1.1 Downstream

Conceptually, the Any-PHY protocol can be divided into two processes: polling

and cell transfer.

Polling in the downstream direction is used by the bus master – typically a traffic

buffering and management device – to determine when a buffered data cell can

be safely sent to a downstream PHY. The S/UNI-VORTEX provides an

independent cell buffer for each logical downstream channel on each LVDS link.

In total there are 256 data path cell buffers (maximum 32 channels per LVDS link

times 8 links) plus 8 microprocessor communication channel buffers (one per

link). This arrangement ensures there is no head of line blocking while

eliminating the risk of buffer overflow.

The traffic manager need only poll those logical channels for which it has

downstream cells queued. A cell transfer can be initiated after a polled logical

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