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PCAL6408APW Datasheet(PDF) 39 Page - NXP Semiconductors |
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PCAL6408APW Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 59 page ![]() NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers 002aag981 DUT CL = 50 pF 500 Pn 2 × VDD(P) 500 a. P port load configuration 002aag982 SCL SDA P0 A tv(Q) 0.3 × VDD(I2C-bus) 0.7 × VDD(I2C-bus) P7 last stable bit unstable data Pn b. Write mode (R/W = 0) 002aag983 SCL Pn P0 A th(D) 0.3 × VDD(I2C-bus) 0.7 × VDD(I2C-bus) P7 0.5 × VDD(P) tsu(D) CL includes probe and jig capacitance. tv(Q) is measured from 0.7 × VDD(I2C-bus) on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. c. Read mode (R/W = 1) Figure 34. P port load circuit and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3.3 — 14 October 2024 Document feedback 39 / 59 |
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