PCAL6408AHKX datasheet(22/59 Pages) NXP

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NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and

configuration registers

VDD(P)

P0 to P7

Configuration

002aah093

DECODER

PMOS_EN0

PMOS_EN1

PMOS_EN2

PMOS_EN3

NMOS_EN3

NMOS_EN2

NMOS_EN1

NMOS_EN0

Output port

Current Control

PMOS_EN[3:0]

NMOS_EN[3:0]

Figure 19. Simplified output stage

Reducing the current drive capability may be desirable to reduce system noise. When the output switches

(transitions from H/L), there is a peak current that is a function of the output drive selection. This peak

current runs through VDD and VSS package inductance and creates noise (some radiated, but more critically

Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time creates ground

and supply noise. The output drive strength control through the Output Drive Strength registers allows the user

to mitigate SSN issues without the need of additional external components.

9.3 Power-on reset requirements

In the event of a glitch or data corruption, PCAL6408A can be reset to its default conditions by using the power-

on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 20 and Figure 21.

002aag960

VDD(P)

time

ramp-up

ramp-down

(dV/dt)r

(dV/dt)f

re-ramp-up

(dV/dt)r

time to re-ramp

when VDD(P) drops

below 0.2 V or to VSS

td(rst)

Figure 20. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD

PCAL6408A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 14 October 2024

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