PCAL6408AHKX datasheet(29/59 Pages) NXP

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NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and

configuration registers

Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ[1] Max

Unit

IIH

HIGH-level input current

P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V

μA

IIL

LOW-level input current

P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V

μA

IDD(I2C-bus) + IDD(P); Operating mode;

SDA, P port, ADDR, RESET;

VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on

P port and ADDR = VDD(P) or VSS; IO = 0 mA; I/O

= inputs; fSCL = 400 kHz

VDD(P) = 3.6 V to 5.5 V

μA

VDD(P) = 2.3 V to 3.6 V

6.5

μA

VDD(P) = 1.65 V to 2.3 V

μA

IDD(I2C-bus) + IDD(P); Standby mode;

SCL, SDA, P port, ADDR, RESET;

VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;

VI on P port and ADDR = VDD(P); IO = 0 mA; I/O =

inputs; fSCL = 0 kHz

VDD(P) = 3.6 V to 5.5 V

1.5

μA

VDD(P) = 2.3 V to 3.6 V

3.2

μA

VDD(P) = 1.65 V to 2.3 V

0.5

1.7

μA

Active mode; IDD(I2C-bus) + IDD(P);

P port, ADDR, RESET;

VI on RESET = VDD(I2C-bus);

VI on P port and ADDR = VDD(P);

IO = 0 mA; I/O = inputs;

fSCL = 400 kHz, continuous register read

VDD(P) = 3.6 V to 5.5 V

125

μA

VDD(P) = 2.3 V to 3.6 V

μA

VDD(P) = 1.65 V to 2.3 V

μA

with pull-ups enabled;

IDD(I2C-bus) + IDD(P); P port, ADDR, RESET;

VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;

VI on P port = VSS;

VI on ADDR = VDD(I2C-bus) or VSS;

IO = 0 mA; I/O = inputs with pull-up enabled; fSCL

= 0 kHz

IDD

supply current

VDD(P) = 1.65 V to 5.5 V

0.55

0.75

SCL, SDA, RESET;

one input at VDD(I2C-bus) - 0.6 V,

other inputs at VDD(I2C-bus) or VSS;

VDD(P) = 1.65 V to 5.5 V

μA

ΔIDD

additional quiescent

supply current[6]

P port, ADDR;

one input at VDD(P) - 0.6 V,

other inputs at VDD(P) or VSS;

μA

Table 23. Static characteristics...continued

PCAL6408A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 14 October 2024

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