MCP6C26 datasheet(24/37 Pages) MICROCHIP

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MCP6C26

DS20006928A-page 26

 2024 Microchip Technology Inc. and its subsidiaries

5.0

APPLICATIONS

This chapter includes design recommendations and

typical application circuits.

The Common-mode rejection (see Figure 2-13,

Figure 2-14, Figure 2-15 and Figure 2-31) supports

high accuracy applications in noisy environments.

The power supply rejection (see Figure 2-32) also has

excellent rejection at higher frequencies than

traditional.

5.1

Recommended Design Practices

Some simple design practices help take advantage of

the MCP6C26's performance in high-side current

sensing applications.

5.1.1

SAFETY PRECAUTIONS

Since the MCP6C26 is used in circuits with voltages

and currents that can be hazardous to humans,

appropriate cautions need to be observed when

designing and using said circuits. Please refer to the

appropriate industry and government standards and

laws to determine design and usage practices.

5.1.2

INPUT VOLTAGE/CURRENT LIMITS

To prevent damage and/or improper operation of these

amplifiers, the circuit must limit the voltages and

currents at and into the VIP and VIM input pins, as well

as the differential input voltage VDM (see Section 1.1,

Absolute Maximum Ratings †). Note that the voltage

limits are independent of the current limits and need

separate attention to ensure these limits.

The ESD protection on the VCM and VDM inputs was

discussed in Section 4.2.1, Internal Protection

Devices. This structure was chosen to protect the input

transistors against many (but not all) overvoltage

conditions, and to minimize input bias currents (IBP and

IBM).

To protect the inputs, always drive VIP with a low

impedance source and use a shunt resistor (RSH) with

low resistance (designed to not fail open). Placing

zener diode(s) or a transorb across RSH will also help

protect the inputs.

5.1.3

BYPASS CAPACITORS

Be sure to specify capacitors that will support your

application. Be sure to look at:

• Voltage Rating (well above the maximum value at

each pin)

• Dielectrics (good Temp. Cos. and reasonable Volt.

Cos.)

•Size

• Surface Mount vs. Leaded

• Cost vs. availability

If possible, connect VSS to ground. This will make your

design simpler.

For both positive and negative single power supply

configurations, bypass VDD to VSS with a local bypass

capacitor next to these pins (e.g., 100 nF). A bulk

bypass capacitor should also be added close by (e.g.,

2.2 μF); placing it next to the local bypass capacitor is

a good choice.

For dual power supply configurations, bypass VDD and

VSS to ground separately with a local bypass capacitor

next to these pins. A bulk bypass capacitor should also

be added close by; placing it next to the local bypass

capacitor is a good choice.

5.1.4

PROTECTING THE INPUTS IN

HIGH-SIDE CURRENT SENSING

APPLICATIONS

Designs using the MCP6C26 will need protection

methods in the circuit design. When working on the

bench, be careful to use the same protection methods

(e.g., do not hot-swap the supply voltages). The

following subsections give ideas that may be useful in

your design.

5.1.4.1

Protecting VDM (VIP - VIM)

The shunt resistor (RSH in Figure 5-1 keeps VDM in

range, as long as the load current is not too high. If

extra protection is needed in your design, ideas to

consider include:

• Limiting VS's output current

• Setting VS's output ESR high enough to reduce

overshoot

- The ESR should be a dynamic resistance,

not a physical one.

5.1.4.2

Protection for Capacitive Loads

Capacitive loads pass large currents when their voltage

changes fast (e.g., at start-up or power down). These

currents will cause voltage drops across resistors and

(parasitic) inductors in the current path. The voltage

drop across inductors can be substantial.

Limiting the current from VS helps protect the circuit in

Figure 5-1. The resistance seen by VS (RS (VS's ESR)

and RCL (CCL's ESR) helps reduce step response over-

shoot, which provides more protection. Using CSH will

create a voltage divider for fast edges; be careful to

limit the resulting VDM.

FIGURE 5-1:

Protection for Capacitive

Loads.

VOUT

–

VSS

CSH

VREF

VDD

(2.7V to 5.5V)

VDD

VIP

VIM

CCL

VS +

–

RCL

VREF

RSH

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