DSP56300 datasheet(58/108 Pages) FREESCALE

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4-10

Viterbi Decoder Implementation

Algorithmic Extensions

Collapsing the States

4.4

COLLAPSING THE STATES

For codes that 0 fill the encoder to create an end of data block, we can reduce the number

of cycles needed to finish the Viterbi decoder processing. Example 4-4 assumes the coder

ends a block by 0 filling the encoder. For the decoder, this means that the last 5 inputs to

a block are known beforehand to take the upper state. There are two cycle-saving

consequences to this. First, we need not update the lower state in the butterflies. Second,

each of the last five inputs creates only half the number of states from the previous input.

For the last input, we update state 0 only, giving us a single starting point for traceback.

The code appears in Example 4-4.

;*****************************************************************

;

PreACSmacro

;

move#BRY,r2

;r2 points to branch metrics

mover5,r3

;save r5 to init r4 later

mover4,n3

;save r4 to init r5 later

movel:(r2)+,ba ;get first branch metrics

movel:(r5)+,y ;load 1st metric/path pair

;

n5,_P_NextStageupdate each state

add y,a

;update metric

add y,b l:(r5)+,y;updt met, ld nxt pair

vsl a,0,l:(r4)+;end top half

;

vsl b,1,l:(r4)+;end 2nd half

movel:(r2)+,ba ;ld br met

_P_NextStage

moven5,b

;recall loop count

asl b

n3,r5

;mult it by 2

mover3,r4

moveb,n5

;storage for loop count

move#BRY,r2

;reinit branch ptr

endm

Example 4-3

Pre-ACS Macro (Continued)

Freescale Semiconductor, Inc.

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