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UM232R Datasheet(PDF) 8 Page - Future Technology Devices International Ltd. |
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UM232R Datasheet(HTML) 8 Page - Future Technology Devices International Ltd. |
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8 / 19 page ![]() UM232R USB-Serial UART Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 Page 8 3.3 Jumper Configuration Options Table 2 - Jumper J1 Pin Description Pin No. Name Type Description 1 3V3 Output 3.3V output from integrated L.D.O. regulator. This pin is decoupled to ground on the module pcb with a 10nF capacitor. The prime purpose of this pin is to provide the internal 3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the FT232RL’s VCCIO pin by connecting this pin to pin 4 (VIO), or by connecting together pins 1 and 2 on jumper J1. 2 VIO PWR +1.8V to +5.25V supply to the UART Interface and CBUS I/O pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect to 3V3 to drive out at 3.3V levels (connect jumper J1 pins 1 and 2 together), or connect to VCC to drive out at 5V CMOS level (connect jumper J1 pins 2 and 3 together). This pin can also be supplied with an external 1.8V - 2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to Vcc. This means that in bus powered designs a regulator which is supplied by the 5V on the USB bus should be used. 3 VCC PWR VCC Output. This will be 5V from the USB bus if pins 1 and 2 on jumper J2 are connected. Alternativly, if the module is in a self powered configuration, the supply to the VCC module pins (15 and 21) will be brought out to this jumper pin. Connect this jumper J1 pin 2 in order to supply the device IO pins from the supply to VCCIO. Table 3 - Jumper J2 Pin Description Pin No. Name Type Description 1 USB PWR 5V Power output USB port. For a low power USB bus powered design, up to 100mA can be sourced from the 5V supply on the USB bus. A maximum of 500mA can be sourced from the USB bus in a high power USB bus powered design. 2 VCC PWR or Output Board supply input. Connect to jumper J2 pin 1 in order to supply the board from the USB bus. This pin is internally connected to the VCC DIP pins. Remove the jumper connector in a self powered design. 3.4 CBUS Signal Options The following options can be configured on the CBUS I/O pins. These options are all configured in the internal EEPROM using the utility software MPROG, which can be downloaded from the FTDI website. The default configuration is described in Section 8. Table 4 - CBUS Signal Options CBUS Signal Option Available On CBUS Pin... Description TXDEN CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Enable transmit data for RS485 PWREN# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Goes low after the device is configured by USB, then high during USB suspend. Can be used to control power to external logic P- Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# pin in this way. TXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Transmit data LED drive - pulses low when transmitting data via USB. See FT232R datasheet for more details. RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Receive data LED drive - pulses low when receiving data via USB. See FT232R datasheet for more details. TX&RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 LED drive - pulses low when transmitting or receiving data via USB. See FT232R datasheet for more details. SLEEP# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Goes low during USB suspend mode. Typically used to power down an external TTL to RS232 level converter I.C. in USB to RS232 converter designs. CLK48 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 48MHz Clock output. CLK24 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 24MHz Clock output. CLK12 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 12MHz Clock output. CLK6 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 6MHz Clock output. CBitBangI/O CBUS0, CBUS1, CBUS2, CBUS3 CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the internal EEPROM. A separate application note will describe in more detail how to use CBUS bit bang mode. BitBangWRn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode WR# strobe Output BitBangRDn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode RD# strobe Output |
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