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AD8362 Datasheet(PDF) 29 Page - Analog Devices

Part # AD8362
Description  50 Hz to 3.8 GHz 65 dB TruPwr™ Detector
PDF  33 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8362 Datasheet(HTML) 29 Page - Analog Devices

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Data Sheet
AD8362
Rev. F | Page 29 of 33
AD8362 EVALUATION BOARD
The AD8362 evaluation board provides for a number of dif-
ferent operating modes and configurations, including many
described in this data sheet. The measurement mode is set up
by positioning SW2 as shown in Figure 67. The AD8362 can be
operated in controller mode by applying the setpoint voltage to
the VSET connector, and flipping SW2 to its alternate position.
The internal voltage reference is used for the target voltage when
SW1 is in the position shown in Figure 67. This voltage may be
reduced optionally via a voltage divider implemented with
R4 and R5, with LK1 in place, and SW1 switched to its alternate
position. Alternatively, an external target voltage may be used
with SW1 switched to its alternate position, LK1 removed, and
the external target voltage applied to the VTGT connector.
In measurement mode, the slope of the response at VOUT may
be increased by using a voltage divider implemented with resis-
tors in Position R17 and Position R9, and with SW2 switched to
its alternate position.
The AD8362 is powered up with SW3 in the position shown in
Figure 67 and connector PWDN open. The device can be powered
down by either connecting a logic high voltage to a connector,
PWDN, with SW3 in the position, or by switching SW3 to its
alternate position.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
AD8362
C6
100pF
C5
100pF
C7
1000pF
C4
1000pF
R15
0Ω
R14
OPEN
C8
1000pF
SW3
R16
OPEN
C10
1000pF
RFIN
PWDN
R13
10kΩ
R17
OPEN
SW2
C3
0.1µF
C9
OPEN
R9
10kΩ
R5
10kΩ
R4
0Ω
R6
0Ω
R7
0Ω
LK1
VREF
VTGT
VOUT
VSET
SW1
R10
0Ω
R8
0Ω
VPOS
R1
0Ω
C2
100pF
C1
0.1µF
AGND
T1
Figure 67. Evaluation Board Schematic



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