TMS470PLF111 datasheet(3/63 Pages) TI

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TMS470PLF111

16/32-BIT RISC FLASH MICROCONTROLLER

SPNS113 – OCTOBER 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

description

The TMS470PLF111(1) devices are members of the Texas Instruments TMS470 family of general-purpose16/

32-bit reduced instruction set computer (RISC) microcontrollers. The PLF111 microcontroller offers high per-

formance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high

instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views

memory as a linear collection of bytes numbered upwards from zero. The TMS470PLF111 utilizes the big-

endian format where the most significant byte of a word is stored at the lowest numbered byte and the least

significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining

low costs. The PLF111 RISC core architecture offers solutions to these performance and cost demands while

maintaining low power consumption.

The real-time interrupt (RTI) module on the PLF111 has the option to be driven by the oscillator clock. The

digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the

watchdog counter expires.

The PLF111 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,

half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented

with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When

in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information

on the flash, see the flash section of this data sheet. The flash on the PLF111 device can be protected by means

of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to

correct single bit errors and detect double bit errors for each 64-bits of data. This is achieved by maintaining

an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory

space.

The PLF111 device has six communication interfaces: SPI, two LINs, CAN (SCC), C2SI, and I2C. The SPI

provides a convenient method of serial interaction for high-speed communications between similar shift-register

type devices. The LIN is the local interconnect network interface which also supports the SCI - a full-duplex,

serial I/O interface intended for asynchronous communication between the CPU and other peripherals using

the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol

that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per

second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., automotive

and industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the

PLF111 to transmit and receive messages on a class II network following an SAE Standard J1850 Class B Data

Communication Network Interface standard. The I2C module is a multi-master communication module providing

an interface between the PLF111 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C

supports both 100 Kbps and 400 Kbps speeds.

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.

The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and

an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well

suited for applications requiring multiple sensor information and drive actuators with complex and accurate

time pulses. The PLF111 HET peripheral contains the XOR-share feature. This feature allows two adjacent

HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard

HET.

The PLF111 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can

be grouped by software for sequential conversion sequences. There are three separate groupings, all three of

which can be triggered by an external event. Each sequence can be converted once when triggered or config-

ured for continuous conversion mode.

1 Throughout the remainder of this document, the TMS470PLF111 shall be referred to as either the full device name or PLF111.

TMS470PLF111 Datasheet(PDF) 3 Page - Texas Instruments

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