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440SP Datasheet(PDF) 1 Page - Applied Micro Circuits Corporation |
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440SP Datasheet(HTML) 1 Page - Applied Micro Circuits Corporation |
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1 / 85 page  Part Number 440SP Revision 1.23 - Sept 26, 2006 AMCC Proprietary 1 PowerPC 440SP Embedded Processor Data Sheet Features •PowerPC‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking) • On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory • Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details) • Supports up to 4 GB (2 Chip Selects) of 64-bit/32- bit SDRAM with ECC – DDR1 266-333-400 – DDR2 400-533-667 • Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support for conventional PCI • XOR Accelerator with DMA controller • Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives • I2O Messaging Unit with two DMA controllers • External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices • One Ethernet 10/100/1000 Mbps half- or full- duplex interface. Operational modes supported are MII and GMII. • Programmable Interrupt Controller supports interrupts from a variety of sources. • Programmable General Purpose Timers (GPT) • Three serial ports (16750 compatible UART) • Two IIC interfaces • General Purpose I/O (GPIO) interface available • JTAG interface for board level testing • Processor can boot from PCI memory Description Designed specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a high- performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O. Technology: CMOS Cu-11, 0.13mm Package: 29mm, 783-ball, 1mm pitch, Flip Chip- Plastic Ball Grid Array (FC-PBGA) Power (estimated): Less than 6W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V |
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