YSS940 datasheet(13/34 Pages) YAMAHA

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YSS944/943/940

(2) On-chip memory access (firmware download)

Access to on-chip memory is performed in 32-bit units via the microprocessor interface. Also, on-chip

memory access can be performed concurrently with register access. The two firmware downloading

methods prepared for this LSI are explained below.

(a) Burst transfer mode

When the IA carrier (PRGMOD[1:0] = 11) is used, instruction code/coefficient data firmware can be

downloaded in this mode. By using this mode, a large amount of data can be downloaded at high speeds

when initialization is executed or when the sampling frequency is changed. The features of the burst

transfer mode are as follows.

• During the transfer period, decoding is aborted and data is transferred at high speeds. Muting is

automatically effected during the transfer period.

• Data transferred from the microprocessor can be received without handshaking.

• Both instruction code firmware and coefficient data firmware can be downloaded.

The microprocessor interface’s sequence in firmware downloading burst transfer mode is shown below.

D28

D29

D30

D31

High-Z

MISO

MISCK

MISI

nMICS

<1>

<2>

A+1

A+n

D28

A+1

<3>

A+n

D29

A+n

D30

A+n

D31

Don't care

<4>

[Access steps and statuses]

<1> Register setting:

The microprocessor interface function change for the on-chip memory access start address (A in

figure) and on-chip memory access is set by register as shown below.

• Set the instruction code firmware download mode (IACNFG = 1)

• Change the firmware program mode to IA carrier (PRGMOD[1:0] = 11).

• Set the on-chip memory access start address IAA[20:0].

• Change the function of the microprocessor interface pin from register access to on-chip memory

access (IA = 1).

Once this setting is made, the microprocessor interface functions in firmware downloading burst

transfer mode until the nMICS pin is set to high level.

<2> Start firmware download:

• The nMICS pin is fixed at low level.

• Data is transferred LSB first, in 32-bit units.

• Data is written to on-chip memory when the rising edge of MISCK occurs for the 32nd bit of data

(D31 in the figure).

<3> Continuation and termination of firmware download:

• Each time 32 bits of data are written, IAA[20:0] is automatically incremented. Accordingly, when

writing to consecutive addresses, only the data is transferred.

• When nMICS changes from low level to high level, firmware download ends and the

microprocessor interface returns to accessing registers.

• When accessing non-consecutive on-chip memory addresses or when resuming firmware

downloading after an access interruption, be sure to set IAA[20:0] as described in <1> above.

<4> When this LSI has not been selected:

<5> Register setting:

After completing a firmware download, perform the following processing.

• Set the instruction code firmware execution mode (IACNFG = 0).

• Report the existence of boot firmware to this LSI (DL = 1).

• Change the firmware program mode PRGMOD[1:0] from “IA carrier” to another mode.

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