8.3 Power Supply Recommendations

The nominal performance of the PGA849 is specified with input-stage supply and output-stage supply voltages

of ±15V, and VICM and VREF at mid-supply. Within the specified limits, custom input common-mode and output

reference voltages can be used without compromising performance; see also Section 6.3. To prevent damage

to internal circuitry, the output-stage power supplies are clamped to stay within the input-stage supply voltage

levels; see also Section 7.2.

CAUTION

Supply voltages higher than 40V (±20V) can permanently damage the device. Parameters that vary

over supply voltage or temperature are shown in Section 6.6 of this data sheet.

8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),

make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.

• Noise can propagate into analog circuitry through the power pins of the device and of the circuit as a whole.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Leakage on the DA_IN+ and DA_IN– pins can cause in a dc offset error in the output voltages. Additionally,

excessive parasitic capacitance at these pins can result in decreased phase margin and affect the stability of

the output stage. If these pins are not used to implement deliberate capacitive feedback, follow best practices

to minimize leakage and parasitic capacitance.

• Follow best practices to minimize leakage and parasitic capacitance, which includes implementing keep-out

areas in any ground planes that lie immediately below the input pins.

• Minimize the number of thermal junctions. If possible, route the signal path using a single layer without vias.

• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not

possible, place the device so that the effects of the thermal energy source on the high and low sides of the

differential signal path are evenly matched.

• Keep the traces as short as possible.

PGA849

SBOSAG3A – MARCH 2024 – REVISED DECEMBER 2024

www.ti.com

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