HT48R54A datasheet(9/40 Pages) HOLTEK

9 / 40 page

HT48R54A

Rev. 1.00

July 27, 2007

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

automatically pushed onto the stack. If the contents of

the status register are important and if the subroutine

can corrupt the status register, precautions must be

taken to save it properly.

Interrupt

The device provides an external interrupt and internal

timer/event counter interrupt. The Interrupt Control Reg-

ister (INTC;0BH) contains the interrupt control bits to set

the enable or disable bits and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be set

to allow interrupt nesting. If the stack is full, the interrupt

request will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented. If immedi-

ate service is desired, the stack must be prevented from

becoming full.

All interrupts have a wake-up capability. When an inter-

rupt is serviced, a control transfer occurs by pushing the

program counter onto the stack, followed by a branch to

a subroutine at specified location in the program mem-

ory. Only the program counter is pushed onto the stack.

If the contents of the register or status register are al-

tered by the interrupt service program, an action which

may corrupt the desired control sequence, the contents

should be saved in advance.

An external interrupt is triggered either on a high to low

or low to high transition on the INT pin. The related inter-

rupt request flag, EIF; bit 4 of the INTC register will then

be set. When the interrupt is enabled, the stack is not full

and the external interrupt is active, a subroutine call to

location 04H will occur. The interrupt request flag (EIF)

and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter 0 interrupt is initialised

by setting the timer/event counter 0 interrupt request

flag, T0F; bit 5 of the INTC register. This will be caused

by a timer 0 overflow. When the interrupt is enabled, the

stack is not full and the T0F bit is set, a subroutine call to

location 08H will occur. The related interrupt request

flag, T0F, will then be reset and the EMI bit cleared to

disable further interrupts.

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation, otherwise C is cleared. C is also affected by a

rotate through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow

from the high nibble into the low nibble in subtraction, otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa, otherwise OV is cleared.

PDF

PDF is cleared by system power-up or executing the

²CLR WDT² instruction. PDF is set by

executing the

²HALT² instruction.

5TO

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction.

TO is set by a WDT time-out.

6, 7

Unused bit, read as

²0²

STATUS (0AH) Register

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1=enable; 0=disable)

EEI

Controls the external interrupt (1=enable; 0=disable)

ET0I

Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)

ET1I

Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)

EIF

External interrupt request flag (1=active; 0=inactive)

T0F

Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

T1F

Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC (0BH) Register

HT48R54A Datasheet(PDF) 9 Page - Holtek Semiconductor Inc

HT48R54A Datasheet(HTML) 9 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL