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HT48R54A Datasheet(PDF) 13 Page - Holtek Semiconductor Inc |
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HT48R54A Datasheet(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 40 page  HT48R54A Rev. 1.00 13 July 27, 2007 To guarantee that the system oscillator is running and stable, the SST (System Start-up Timer) provides an ex- tra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or when the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack R E S V D D 1 0 0 k W 1 0 k W 0 . 1 m F 0 . 0 1 m F R E S V D D 1 0 0 k W 0 . 1 m F B a s i c R e s e t C i r c u i t H i - n o i s e R e s e t C i r c u i t Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. The states of the registers are summarised in the table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu MODE ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² |
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