SC2544 datasheet(15/24 Pages) SEMTECH

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SC2544

POWER MANAGEMENT

The conduction losses are then

bc=IQ2,rms

ds(on).

where R

ds(on) is the channel resistance of bottom

MOSFET. If the input voltage to output voltage ratio

is high (e.g. V

in=12V, Vo=1.5V), the duty ratio D will

be small. Since the bottom switch conducts with duty

ratio (1-D), the corresponding conduction losses can

be quite high.

Due to non-overlapping conduction between the top and

the bottom MOSFET’s, the internal body diode or the

external Schottky diode across the drain and source

terminals always conducts prior to the turn on of the

bottom MOSFET. The bottom MOSFET switches on with

only a diode voltage between its drain and source

terminals. The switching loss is negligible due to near zero-

voltage switching.

The gate losses are estimated as

Bottom Switch

The RMS current in bottom switch is given by

)

)(

(

rms

−

The total bottom switch losses are then

b=Pbc+Pbg.

Main Control Loop Design

The goal of compensation is to shape the frequency

response charatericstics of the buck converter to

achieve a better DC accuracy and a faster transient

response for the output voltage, while maintaining

the loop stability.

The block diagram in Figure 10 represents the control

loop of a buck converter designed with the SC2544. The

control loop consists of a compensator, a PWM modula-

tor, and an LC filter.

The LC filter and PWM modulator represent the small

signal model of the buck converter operating at fixed

switching frequency. The transfer function of the

model is given by:

ESR

⋅

bg =

Once the power losses for the top and bottom

MOSFET’s are known, thermal and package design

at component and system level should be done to

verify that the maximum die junction temperature

j,max, usually 125

C) is not exceeded under the

worst-case condition.

The equivalent thermal

impedance from junction to ambient (

ja) should

satisfy

depends on the die to substrate bonding,

packaging material, the thermal contact surface,

thermal compound property, the available effective

heat sink area, and the air flow condition (natual or

forced convection). Actual temperature measurement

of the prototype should be carried out to verify the

thermal design.

loss

max

−

≤

REF

Resr

REF

MODULATOR

PWM

ERROUT

Fig. 10. Block diagram of the control loop.

where V

IN is the input voltage, Vm is the amplitude of

the internal ramp, and R is the equivalent load.

The model is a second order system with a finite DC

gain, a complex pole pair at Fo, and an ESR zero at

Fz, as shown in Figure 11. The locations of the poles

and zero are determined by:

Applications Information (Cont.)

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