TMS320DM6437 datasheet(8/309 Pages) TI

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TMS320DM6437

Digital Media Processor

SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 3.7

Section 3.7, Multiplexed Pin Configurations:

Figure 3-11, Pin Mux Block Selection:

Updated/Changed "B. EMIFA/VPSS Block:" footnote for clarity

Section 3.6.1

Section 3.6.1, Switch Central Resource (SCR) Bus Priorities:

Added Table 3-14, MSTPRI0 Register Bit Description

Added Table 3-15, MSTPRI1 Register Bit Description

Section 3.7.1

Section 3.7.1, Pin Muxing Selection At Reset:

EMIFA/VPSS Block bullet:

Updated/Changed sub-bullets "AEM[2:0] = 000b, 011b, 100b, and 101b to "... AEAW[2:0] = don't care ..."

Section 3.7.2.2

Section 3.7.2.2, PINMUX1 Register Description:

Figure 3-13, PINMUX1 Register:

Updated/Changed the LEGEND for Bit 0, "PCIEN" from "R/W-P" to "R-P".

Table 3-20, PINMUX1 Register Bit Descriptions:

Added the "The PCIMUX.PCIEN reflects the state of the PCIEN ..." paragraph to the Bit 0, PCIEN

description.

Section 3.7.3.1

Section 3.7.3.1, Multiplexed Pins on DM6437:

Table 3-21, Multiplexed Pins on DM6437:

Updated/Changed the "R1/EM_BA[0]/GP[7]/(AEM2)" signal name to "R1/EM_A[0]/GP[7]/(AEM2)"

Section 3.7.3.8

Section 3.7.3.8, Timer0 Block:

Added "GPIO" to the "This block of 2 pins consists of ... muxed pins." paragraph.

Section 3.7.3.9

Section 3.7.3.9, Timer1 Block:

Added "GPIO" to the "This block of 2 pins consists of ... muxed pins." paragraph.

Section 3.7.3.13.3

Section 3.7.3.13.3, EMIFA/VPSS Sub-Block 0 Configuration Choices:

After Table 3-49, EMIFA/VPSS Sub-Block 0 Configuration Choice G:

Updated/Changed "The PINMUX Selection Fields columns indicate ..." bullet from "... (based on the

system's need for VPBE ..." to "... (based on the system's need for VPFE ..."

Section 3.7.3.13.4

Section 3.7.3.13.4, EMIFA/VPSS Sub-Block 1 Configuration Choices:

Added "and VPBECKEN" to step 3. "Within the chosen Minor Configuration Option, ..."

Section 3.8

Section 3.8, Device Initialization Sequence After Reset:

Added "Special Considerations:" paragraph to step 8.a.

Section 6.3.4

Section 6.3.4, DM6437 Power and Clock Domains:

Updated/Changed Figure 6-5, PLL1 Structure Block Diagram

Section 6.4.2

Section 6.4.2, EDMA Peripheral Register Description(s):

Table 6-7, DM6437 EDMA Registers:

Added 0x01C0 0608 "QSTAT2" "Queue 2 Status Register"

Added "Command" to the register name for all RDRATE registers

Deleted "Source" from all SABIDX register names

Updated/Changed "BIDX" to "B-Index" for DFBIDX0 through DFBIDX3 register names

Section 6.5.3

Section 6.5.3, Maximum Reset:

Added "To invoke the maximum reset via the ICEPICK ..." sentence before the Max Reset Sequence

Section 6.8

Section 6.8, Interrupts:

Updated document reference in the "For more details on DSP interrupt ..." sentence

Deleted "and the generation of AEG events" from the "Also, the interrupt controller controls the generation

..." sentence

Updated/Changed "Table 6-21. DM6437 DSP Interrupts" title to "Table 6-21. DM6437 DSP System

Event Mapping"

Updated/Changed "DSP Interrupt Number" column header to "DSP System Event Number"

Revision History

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