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TMS320DM6437 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM6437 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 309 page  www.ti.com 1 TMS320DM6437 Digital Media Processor 1.1 Features TMS320DM6437 Digital Media Processor SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007 RAM/Cache [Flexible Allocation] • High-Performance Digital Media Processor (DM6437) – 640K-Bit (80K-Byte) L1D Data RAM/Cache – 2.5-, 2.-, 1.67-ns Instruction Cycle Time [Flexible Allocation] – 400-, 500-, 600-MHz C64x+™ Clock Rate – 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] – Eight 32-Bit C64x+ Instructions/Cycle – 3200, 4000, 4800 MIPS • Supports Little Endian Mode Only – Fully Software-Compatible With C64x • Video Processing Subsystem (VPSS) – Commercial and Extended Temperature – Front End Provides: Ranges • CCD and CMOS Imager Interface • VelociTI.2™ Extensions to VelociTI™ • BT.601/BT.656 Digital YCbCr 4:2:2 Advanced Very-Long-Instruction-Word (VLIW) (8-/16-Bit) Interface TMS320C64x+™ DSP Core • Preview Engine for Real-Time Image – Eight Highly Independent Functional Units Processing With VelociTI.2 Extensions: • Glueless Interface to Common Video • Six ALUs (32-/40-Bit), Each Supports Decoders Single 32-Bit, Dual 16-Bit, or Quad 8-Bit • Histogram Module Arithmetic per Clock Cycle • Auto-Exposure, Auto-White Balance and • Two Multipliers Support Four 16 x 16-Bit Auto-Focus Module Multiplies (32-Bit Results) per Clock • Resize Engine Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Resize Images From 1/4x to 4x Results) per Clock Cycle • Separate Horizontal/Vertical Control – Load-Store Architecture With Non-Aligned – Back End Provides: Support • Hardware On-Screen Display (OSD) – 64 32-Bit General-Purpose Registers • Four 54-MHz DACs for a Combination of – Instruction Packing Reduces Code Size • Composite NTSC/PAL Video – All Instructions Conditional • Luma/Chroma Separate Video – Additional C64x+™ Enhancements (S-video) • Protected Mode Operation • Component (YPbPr or RGB) Video • Exceptions Support for Error Detection (Progressive) and Program Redirection • Digital Output • Hardware Support for Modulo Loop • 8-/16-bit YUV or up to 24-Bit RGB Auto-Focus Module Operation • HD Resolution • C64x+ Instruction Set Features • Up to 2 Video Windows – Byte-Addressable (8-/16-/32-/64-Bit Data) • External Memory Interfaces (EMIFs) – 8-Bit Overflow Protection – 32-Bit DDR2 SDRAM Memory Controller – Bit-Field Extract, Set, Clear With 256M-Byte Address Space (1.8-V I/O) – Normalization, Saturation, Bit-Counting – Asynchronous 8-Bit Wide EMIF (EMIFA) – VelociTI.2 Increased Orthogonality With up to 64M-Byte Address Reach – C64x+ Extensions • Flash Memory Interfaces • Compact 16-bit Instructions • NOR (8-Bit-Wide Data) • Additional Instructions to Support • NAND (8-Bit-Wide Data) Complex Multiplies • Enhanced Direct-Memory-Access (EDMA) • C64x+ L1/L2 Memory Architecture Controller (64 Independent Channels) – 256K-Bit (32K-Byte) L1P Program • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the Copyright © 2006–2007, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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