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GL9711 Datasheet(PDF) 22 Page - GENESYS LOGIC |
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GL9711 Datasheet(HTML) 22 Page - GENESYS LOGIC |
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22 / 42 page  GL9711 PCI Express TM PIPE x1 PHY ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 22 1 SKPDEL Enable SKP deleting test of SKP ordered sets 0 SKPADD Enable SKP adding test of SKP ordered sets Offset 0Dh – SLCDT ………...…………………………………………...……. Default value = 8’h00 -- SLPBK -- -- -- FENCD -- -- -- R/W -- -- -- R/W -- -- 7 RESERVED - 6 SLPBK Enable serial loopback 5-3 RESERVED - 2 FENCD Force comma detect 1-0 RESERVED - 4.3 SMBus Protocal GL9711 registers are programmed by System Management Bus (SMBus). Fig. 4.1 shows the SMBus topology. The VDD power is 2.5V +/- 10% and the pull up resistor is 1KΩ. Both SMBCLK and SMBDAT lines are bi-directional, connected to 2.5V supply voltage through a pull-up resistor. The operating frequency is 10~100KHz and the SMBus address of GL9711 is 7’h2C. Figure 4.1 – SMBus Topology of GL9711 |
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