TMS28F008AXY datasheet(14/52 Pages) TI

14 / 52 page

TMS28F008Axy,TMS28F800Axy

1 048 576 BY 8-BIT/524 288 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

operation (continued)

Table 3. CSM Codes for Device-Mode Selection

COMMAND

CODE ON

DQ0–DQ7†

DEVICE MODE

00h

10h

20h

40h

50h

70h

90h

B0h

D0h

FFh

Invalid/Reserved

Alternate Program Setup

Block-Erase Setup

Program Setup

Clear Status Register

Read Status Register

Algorithm Selection

Erase-Suspend

Erase-Resume/Block-Erase Confirm

Read Array

† DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state

level.

command definition

Once a specific command code has been entered, the WSM executes an internal algorithm generating the

necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and

data for each of the bus cycles.

Table 4. Command Definitions

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

COMMAND

CYCLES

REQUIRED

OPERATION

ADDRESS

DATA

INPUT

OPERATION

ADDRESS

DATA

IN/OUT

Read Operations

Read Array

Write

FFh

Read

Data Out

Read Algorithm-Selection Code

Write

90h

Read

M/D

Read Status Register

Write

70h

Read

SRB

Clear Status Register

Write

50h

Program Mode

Program Setup / Program

(byte / word)

Write

40h or 10h

Write

Erase Operations

Block-Erase Setup/

Block-Erase Confirm

Write

BEA

20h

Write

BEA

D0h

Erase Suspend/

Erase Resume

Write

B0h

Write

D0h

Legend:

BEA

Block-erase address. Any address selected within a block selects that block for erase.

M / D

Manufacturer-equivalent/ device-equivalent code

Address to be programmed

Data to be programmed at PA

SRB

Status-register data byte that can be found on DQ0 – DQ7

Don’t care

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