MPC8280_07 datasheet(130/1386 Pages) FREESCALE

130 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-14

Freescale Semiconductor

2.3.1.2.2

Hardware Implementation-Dependent Register 1 (HID1)

The MPC8280 implementation of HID1 is shown in Figure 2-4.

Table 2-2 shows the bit definitions for HID1.

2.3.1.2.3

Hardware Implementation-Dependent Register 2 (HID2)

The processor core implements an additional hardware implementation-dependent register, shown in

Figure 2-5.

29–30

—

Reserved

NOOPTI

No-op the data cache touch instructions.

0The dcbt and dcbtst instructions are enabled.

1The dcbt and dcbtst instructions are no-oped globally.

See Chapter 10, “Power Management

,” of the G2 Core Reference Manual for more information.

See Chapter 4, “Instruction and Data Cache Operation

,” of the G2 Core Reference Manual for more information.

PLLCFG

—

Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)

Table 2-2. HID1 Field Descriptions

Bits

Name

Function

0–4

PLLCFG PLL configuration setting. These bits reflect the state of the PLL_CFG[0:4] signals.

5–31

—

Reserved

141516

18 19

—

HBE —

SFP

IWLCK

—

DWLCK

—

Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)

Table 2-1. HID0 Field Descriptions (continued)

Bits

Name

Description

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