LTC7892 datasheet(42/50 Pages) AD

42 / 50 page

Data Sheet

LTC7892

analog.com

Rev. 0

42 of 50

Select the RSENSE resistor value. The peak inductor current is the maximum DC output current plus half the

inductor ripple current, or 8A x (1 + 0.31 / 2) = 9.24A in this case. The RSENSE resistor value is then calculated

based on the minimum value for the maximum current sense threshold (45mV for ILIM = float) given by

Equation 27, as follows:

RSENSE ≤

45mV

9.24A

≈ 4

mΩ

(27)

To allow for additional margin, a lower value RSENSE can be used. However, be sure that the inductor

saturation current has a sufficient margin above VSENSE(MAX)/ RSENSE, where the maximum value of 55mV is used

for VSENSE(MAX).

Select the feedback resistors. Choosing 1% resistors: RA = 5kΩ and RB = 95.3kΩ yields an output voltage of

24.07V. The resistance values selected give a feedback divider current of 24.07V / (5kΩ + 95.3kΩ) = 240µA.

Select the FETs. The best way to evaluate FET performance in a particular application is to build and test the

circuit on the bench, facilitated by an LTC7892 evaluation board. However, an educated guess about the

application is helpful to initially select FETs. Because this is a high current, low voltage application, I2R losses

will likely dominate over transition losses for the bottom FET. Therefore, choose a FET with a lower RDS(ON) as

opposed to a lower gate charge to minimize the combined loss terms. The top FET does not experience

transition losses, and its power loss is generally dominated by I2R losses. For this reason, the top FET is

typically chosen to have a lower RDS(ON) and subsequently, higher gate charge than the bottom FET.

When using silicon MOSFETs, be sure to select logic level threshold MOSFETs because the gate drive voltage

is limited to 5.5V (INTVCC).

Select the output capacitor. COUT is chosen to filter the square current in the output. The maximum output

current peak is given by Equation 28, as follows:

IOUT(PEAK) = IOUT(MAX) • (1 +

RIPPLE%

) = 4 • (1 +

31%

) = 4.62A

(28)

A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 23.1mV (assuming

ESR dominates the ripple).

Determine the bias supply components. If another supply is available that is above the INTVCC regulation

voltage and below VIN, for example, an 8.5V supply, connect that supply to EXTVCC to improve the efficiency.

For a 6.7ms soft start, select a 0.1μF capacitor for the SSx pin. As a first-pass estimate for the bias

components, select the INTVCC capacitance (CINTVCC) = 4.7μF and boost supply capacitor (CB)= 0.1μF.

10.

Determine and set application-specific parameters. Set the MODE pin based on the trade-off of light load

efficiency and constant frequency operation. Set the PLLIN/SPREAD pin based on whether a fixed, spread

spectrum, or phase-locked frequency is desired. The RUNx pin can be used to control the minimum input

voltage for regulator operation or can be tied to VIN for always-on operation. Use ITHx compensation

components from the typical applications as a first guess, check the transient response for stability, and

modify as necessary. Program the DTCA and DTCB pins for the desired dead time delays.

LTC7892 Datasheet(PDF) 42 Page - Analog Devices

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