LTC7890 datasheet(11/50 Pages) AD

11 / 50 page

Data Sheet

LTC7892

analog.com

Rev. 0

11 of 50

RUN2

Run Control Input for Channel 2. Forcing RUN2 less than 1.08V disables controller

switching. Forcing RUN1 and RUN2 less than 0.7V shuts down the LTC7892, reducing IQ

to approximately 1μA. Tie the RUN2 pin to VBIAS to ensure it is always in operation.

GND

Ground. The GND pin and the exposed pad must be soldered to PCB ground for rated

electrical and thermal performance.

DRVUV

DRVCC UVLO and EXTVCC Switchover Program Pin. DRVUV determines the INTVCC UVLO

and EXTVCC switchover rising and falling thresholds, as listed in Table 1.

DRVSET

INTVCC Regulation Program Pin. DRVSET sets the regulation point for the INTVCC LDO

linear regulators. Connect DRVSET to GND to set INTVCC to 5V. Connect DRVSET to

INTVCC to set INTVCC to 5.5V. Program voltages between 4V and 5.5V by placing a

resistor (43kΩ to 110kΩ) between DRVSET and GND. The resistor and an internal 20μA

source current create a voltage used by the INTVCC LDO regulator to set the regulation

point.

DTCA

Dead Time Control Pin for Bottom FET Off to Top FET On Delay. Connect DTCA to GND

to program an adaptive dead time delay of approximately 15ns. Connect a resistor

between DTCA and GND to program a nonadaptive (open-loop) dead time delay from

7ns to 60ns.

DTCB

Dead Time Control Pin for Top FET Off to Bottom FET On Delay. Connect to GND to

program an adaptive TG off to BG on a dead time delay of approximately 15ns.

Connect a resistor between DTCB and GND to program a nonadaptive (open-loop) TG

off to BG on dead time from 7ns to 60ns.

SENSE2+

Positive Input to the Differential Current Comparator for Channel 2. The SENSE2+ pin

supplies current to the current comparator for Channel 2 when SENSE2+ is greater than

INTVCC.

SENSE2-

Negative Input to the Differential Current Comparator for Channel 2. The ITH2 pin

voltage and controlled offset between the SENSE2+ and SENSE2- pins, in conjunction

with the current sense resistor (RSENSE), set the current trip threshold.

VFB2

Error Amplifier Feedback Input for Channel 2. VFB2 Receives the remotely sensed

feedback voltage for channel 2 from an external resistive divider across the output. Tie

VFB2 to INTVCC for a 2-phase single output application, in which both channels share

VFB1, ITH1, and SS1.

ITH2

Error Amplifier Output and Switching Regulator Compensation Point for Channel 2.

The current comparator trip point increases with this control voltage.

SS2

External Soft Start Input for Channel 2. SS2 regulates the VFB2 voltage to the lesser of

1.2V or the voltage on the SS2 pin. An internal 12μA pull-up current source is

connected to SS2. A capacitor to GND at SS2 sets the ramp time to the final regulated

output voltage. The ramp time is equal to 1ms for every 10nF of capacitance.

ILIM

Current Comparator Sense Voltage Range Input. Tying ILIM to GND or INTVCC or floating

it sets the maximum current sense threshold to one of three different levels (25mV,

75mV, and 50mV, respectively).

PGOOD2

Power Good Open-Drain Logic Output for Channel 2. PGOOD2 is pulled to the ground

when the voltage on VFB2 is not within ±10% of its set point.

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