ADC10464 datasheet(14/17 Pages) NSC

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Applications Information (Continued)

4.0 INHERENT SAMPLE-AND-HOLD

Because the ADC10461, ADC10462, and ADC10464

sample the input signal once during each conversion, they

are capable of measuring relatively fast input signals without

the help of an external sample-hold. In a non-sampling

successive-approximation A/D converter, regardless of

speed, the input signal must be stable to better than ±1/2

LSB during each conversion cycle or significant errors will

result. Consequently, even for many relatively slow input

signals, the signals must be externally sampled and held

constant during each conversion if a SAR with no internal

sample-and-hold is used.

Because they incorporate a direct sample/hold control input,

the ADC10461, ADC10462, and ADC10464 are suitable for

use in DSP-based systems. The S/H input allows synchro-

nization of the A/D converter to the DSP system’s sampling

rate

and

other

ADC10461s,

ADC10462s,

and

ADC10464s.

5.0 POWER SUPPLY CONSIDERATIONS

The ADC10461, ADC10462, and ADC10464 are designed to

operate from a +5V (nominal) power supply. There are two

supply pins, AV

CC and DVCC. These pins allow separate

external bypass capacitors for the analog and digital portions

of the circuit. To guarantee accurate conversions, the two

supply pins should be connected to the same voltage

source, and each should be bypassed with a 0.1 µF ceramic

capacitor in parallel with a 10 µF tantalum capacitor. De-

pending upon the circuit board layout and other system

considerations, more bypassing may be necessary.

The ADC10461 has a single ground pin, and the ADC10462

and ADC10464 each have separate analog and digital

ground pins for separate bypassing of the analog and digital

supplies. The devices with separate analog and digital

ground pins should have their ground pins connected to the

same potential, and all grounds should be “clean” and free of

noise.

In systems with multiple power supplies, careful attention to

power supply sequencing may be necessary to avoid over-

driving inputs. The A/D converter’s power supply pins should

be at the proper voltage before digital or analog signals are

applied to any of the other pins.

6.0 LAYOUT AND GROUNDING

In order to ensure fast, accurate conversions from the

ADC10461, ADC10462, and ADC10464, it is necessary to

use appropriate circuit board layout techniques. The analog

ground return path should be low-impedance and free of

noise from other parts of the system. Noise from digital

circuitry can be especially troublesome.

All bypass capacitors should be located as close to the

converter as possible and should connect to the converter

and to ground with short traces. The analog input should be

isolated from noisy signal traces to avoid having spurious

signals couple to the input. Any external component (e.g., a

filter capacitor) connected across the converter’s input

should be connected to a very clean ground return point.

Grounding the component at the wrong point will result in

reduced conversion accuracy.

7.0 DYNAMIC PERFORMANCE

Many applications require the A/D converter to digitize AC

signals, but conventional DC integral and differential nonlin-

earity specifications don’t accurately predict the A/D convert-

er’s performance with AC input signals. The important speci-

fications for AC applications reflect the converter’s ability to

digitize AC signals without significant spectral errors and

without adding noise to the digitized signal. Dynamic char-

acteristics such as signal-to-noise ratio (SNR) and total har-

monic distortion (THD), are quantitative measures of this

capability.

An A/D converter’s AC performance can be measured using

Fast Fourier Transform (FFT) methods. A sinusoidal wave-

form is applied to the A/D converter’s input, and the trans-

form is then performed on the digitized waveform. The re-

sulting spectral plot might look like the ones shown in the

typical performance curves. The large peak is the fundamen-

tal frequency, and the noise and distortion components (if

any are present) are visible above and below the fundamen-

tal frequency. Harmonic distortion components appear at

whole multiples of the input frequency. Their amplitudes are

combined as the square root of the sum of the squares and

compared to the fundamental amplitude to yield the THD

specification. Guaranteed limits for THD are given in the

table of Electrical Characteristics.

Signal-to-noise ratio is the ratio of the amplitude at the

fundamental frequency to the rms value at all other frequen-

cies, excluding any harmonic distortion components. Guar-

anteed limits are given in the Electrical Characteristics table.

An alternative definition of signal-to-noise ratio includes the

distortion components along with the random noise to yield a

signal-to-noise-plus-distortion ration, or S/(N + D).

The THD and noise performance of the A/D converter will

change with the frequency of the input signal, with more

distortion and noise occurring at higher signal frequencies.

One way of describing the A/D’s performance as a function

of signal frequency is to make a plot of “effective bits” versus

frequency. An ideal A/D converter with no linearity errors or

self-generated noise will have a signal-to-noise ratio equal to

(6.02n + 1.76) dB, where n is the resolution in bits of the A/D

converter. A real A/D converter will have some amount of

noise and distortion, and the effective bits can be found by:

where S/(N + D) is the ratio of signal to noise and distortion,

which can vary with frequency.

As an example, an ADC10461 with a 4.85 V

P-P, 100 kHz

sine wave input signal will typically have a signal-to-noise-

plus-distortion ratio of 59.2 dB, which is equivalent to 9.54

effective bits. As the input frequency increases, noise and

distortion gradually increase, yielding a plot of effective bits

or S/(N + D) as shown in the typical performance curves.

8.0 SPEED ADJUST

In applications that require faster conversion times, the

Speed Adjust pin (pin 14 on the ADC10462, pin 17 on the

ADC10464) can significantly reduce the conversion time.

The speed adjust pin is connected to an on-chip current

source that determines the converter’s internal timing. By

connecting a resistor between the speed adjust pin and

ground as shown in Figure 4, the internal programming

current is increased, which reduces the conversion time. As

an example, an 18k resistor reduces the conversion time of

a typical part from 600 ns to 350 ns with no significant effect

on linearity. Using smaller resistors to further decrease the

conversion time is possible as well, although the linearity will

begin to degrade somewhat (see curves). Note that the

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