LPC2364 datasheet(21/47 Pages) NXP

21 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

21 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

7.13 10-bit DAC

The DAC allows the LPC2364/66/68 to generate a variable analog output. The maximum

output value of the DAC is Vi(VREF).

7.13.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.14 UARTs

The LPC2364/66/68 each contain four UARTs. In addition to standard transmit and

receive data lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as 115200

can be achieved with any crystal frequency above 2 MHz.

7.14.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software ﬂow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware ﬂow control (auto-CTS/RTS).

• UART3 includes an IrDA mode to support infrared communication.

7.15 SPI serial I/O controller

The LPC2364/66/68 each contain one SPI controller. SPI is a full duplex serial interface

designed to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and

the slave always sends 8 bits to 16 bits of data to the master.

7.15.1 Features

• Compliant with SPI speciﬁcation

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

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