LPC2364 datasheet(30/47 Pages) NXP

30 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

30 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

7.25 System control

7.25.1 Reset

Reset has four sources on the LPC2364/66/68: the RESET pin, the Watchdog reset,

power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains

a usable level, starts the Wake-up timer (see description in Section 7.24.3 “Wake-up

timer”), causing reset to remain asserted until the external Reset is de-asserted, the

oscillator is running, a ﬁxed number of clocks have passed, and the ﬂash controller has

completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.25.2 Brownout detection

The LPC2364/66/68 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this

voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the

VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC2364/66/68

when the voltage on the VDD(3V3) pins falls below 2.65 V. This Reset prevents alteration of

the ﬂash as operation of the various elements of the chip would otherwise become

unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at

which point the power-on reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.25.3 Code security

This feature of the LPC2364/66/68 allows an application to control whether it can be

debugged or protected from observation.

If after reset the on-chip bootloader detects a valid checksum in ﬂash and reads

0x8765 4321 from address 0x1FC in ﬂash, debugging will be disabled and thus the code

in ﬂash will be protected from observation. Once debugging is disabled, it can be enabled

by performing a full chip erase using the ISP.

7.25.4 AHB bus

The LPC2364/66/68 implements two AHB buses in order to allow the Ethernet block to

operate without interference caused by other system activity. The primary AHB, referred to

as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface,

and 8 kB SRAM primarily intended for use by the USB.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

unused space in memory residing on AHB1.

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