LPC2364 datasheet(24/47 Pages) NXP

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LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

24 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

7.20 General purpose 32-bit timers/external event counters

The LPC2364/66/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to

count cycles of the system derived clock or an externally-supplied clock. It can optionally

generate interrupts or perform other actions at speciﬁed timer values, based on four

match registers. The Timer/Counter also includes two capture inputs to trap the timer

value when an input signal transitions, optionally generating an interrupt.

7.20.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Counter or Timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.21 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2364/66/68. The Timer is designed to

count cycles of the system derived clock and optionally switch pins, generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match registers.

The PWM function is in addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

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