MAX1067BEEE datasheet(21/30 Pages) MAXIM

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DSP 8-Bit-Wide Data-Transfer Mode (External Clock

Mode, MAX1068 Only)

Figure 16 shows the DSP-interface timing diagram.

Logic low at DSPR on the falling edge of CS enables

DSP interface mode. After the MAX1068 enters DSP

mode, CS can remain low for the duration of the con-

version process and each subsequent conversion.

Drive DSEL low to select the 8-bit data-transfer mode.

A sync pulse from the DSP at DSPR wakes the analog

circuitry and allows SCLK to clock in data (Figure 17).

The frame sync pulse alerts the MAX1068 that incom-

ing data is about to be sent to DIN. Ensure the duty

cycle on SCLK is between 45% and 55% when operat-

ing at 4.8MHz (the maximum clock frequency). For

lower clock frequencies, ensure the minimum high and

low times are at least 93ns. External clock mode con-

versions with SCLK rates less than 125kHz can reduce

accuracy due to leakage of the sampling capacitor.

The input data latches on the falling edge of SCLK. The

command/configuration/control register starts reading

data in on the falling edge of the first SCLK cycle imme-

diately following the falling edge of the frame sync

pulse and ends on the falling edge of the 8th SCLK

cycle. The MAX1068 selects the proper channel for

conversion on the falling edge of the 3rd clock cycle

and begins acquisition. Acquisition continues until the

rising edge of the 7th clock cycle. The MAX1068 sam-

ples the input on the rising edge of the 7th clock cycle.

On the rising edge of the 8th clock cycle, the MAX1068

outputs a frame sync pulse at DSPX. The frame sync

pulse alerts the DSP that the conversion results are

about to be output at DOUT (MSB first) starting on the

rising edge of the 9th clock pulse. To read the entire

conversion results, 16 SCLK cycles are needed. Extra

clock pulses, occuring after the conversion result has

been clocked out, and prior to the next rising edge of

DSPR, cause zeros to be clocked out of DOUT. The

MAX1068 external-clock, DSP 8-bit-wide data-transfer

mode requires 24 clock cycles to complete.

Begin a new conversion by sending a new frame sync

pulse to DSPR followed by new configuration data.

Send the new DSPR pulse immediately after reading

the conversion result to realize maximum throughput.

Sending a new frame sync pulse in the middle of a con-

version immediately aborts the current conversion and

begins a new one. A rising edge on CS in the middle of

a conversion aborts the current conversion and places

the MAX1068 in shutdown.

DSP 16-Bit-Wide Data-Transfer Mode (External

Clock Mode, MAX1068 Only)

Figure 16 shows the DSP-interface timing diagram. Logic

low at DSPR on the falling edge of CS enables DSP inter-

face mode. After the MAX1068 enters DSP mode, CS

can remain low for the duration of the conversion

process and each subsequent conversion. The acquisi-

tion time is extended an extra eight SCLK cycles in the

16-bit-wide data-transfer mode. Drive DSEL high to

select the 16-bit-wide data-transfer mode. A sync pulse

from the DSP at DSPR wakes the analog circuitry and

allows SCLK to clock in data (Figure 18). The frame

sync pulse also alerts the MAX1068 that incoming data

is about to be sent to DIN. Ensure the duty cycle on

SCLK is between 45% and 55% when operating at

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

______________________________________________________________________________________

SCLK

DSPR

DIN

DOUT

tCSS

tCL

tDS

tDH

tDV

tCH

tDO

tTR

tFSH

tCSH

tDF

tCP

tCSW

tFSS

...

Figure 16. Detailed DSP-Interface Timing (MAX1068 Only)

MAX1067BEEE Datasheet(PDF) 21 Page - Maxim Integrated Products

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