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TMS320DM6467 Datasheet(PDF) 49 Page - Texas Instruments

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Part # TMS320DM6467
Description  Digital Media System-on-Chip
PDF  334 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM6467 Datasheet(HTML) 49 Page - Texas Instruments

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TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
Table 2-16. Video-Port Interface (VPIF) Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
VIDEO-PORT INTERFACE (VPIF) – CAPTURE
IPD
VP_CLKIN0
AC13
I
VPIF capture channel 0 input clock (I).
DVDD33
IPD
VP_CLKIN1
AB18
I
VPIF capture channel 1 input clock (I).
DVDD33
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN15_VP_VSYNC/
IPD
AC18
I
When used for the VPIF, this pin is capture data bit 15 or the vertical sync
TS0_DIN7
DVDD33
input, VP_DIN15_VSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN14_VP_HSYNC/
IPD
AA17
I
When used for the VPIF, this pin is capture data bit 14 or the horizontal sync
TS0_DIN6
DVDD33
input, VP_DIN14_HSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN13_FIELD/
IPD
AB17
I
When used for the VPIF, this pin is capture data bit 13 or the field indicator
TS0_DIN5
DVDD33
input, VP_DIN13_FIELD (I).
VP_DIN12/
AC17
TS0_DIN4
VP_DIN11/
Y16
TS0_DIN3
VP_DIN10/
IPD
These pins are multiplexed between the VPIF and TSIF0.
AA16
I
TS0_DIN2
DVDD33
When used for the VPIF, these pins are capture data bits, VP_DIN[12:8] (I).
VP_DIN9/
AB16
TS0_DIN1
VP_DIN8/
AC16
TS0_DIN0
VP_DIN7/
TS0_DOUT7/
Y14
TS1_DIN
VP_DIN6/
TS0_DOUT6/
AA14
TS1_PSTIN
IPD
These pins are multiplexed between the VPIF, TSIF0, and TSIF1.
I/O/Z
DVDD33
When used for the VPIF, these pins are capture data bits, VP_DIN[7:4] (I).
VP_DIN5/
TS0_DOUT5/
AB14
TS1_EN_WAITO
VP_DIN4/
TS0_DOUT4/
AC14
TS1_WAITO
VP_DIN3/
Y15
TS0_DOUT3
VP_DIN2/
AA15
TS0_DOUT2
IPD
These pins are multiplexed between the VPIF and TSIF0.
I/O/Z
DVDD33
When used for the VPIF, these pins are capture data bits, VP_DIN[3:0] (I).
VP_DIN1/
AB15
TS0_DOUT1
VP_DIN0/
AC15
TS0_DOUT0
VIDEO-PORT INTERFACE (VPIF) – DISPLAY
IPD
VP_CLKIN2
Y10
I
VPIF display channel 2 source input clock (I).
DVDD33
This pin is multiplexed between the VPIF and TSIF1.
VP_CLKIN3/
IPD
AC9
I/O/Z
When used for VPIF, this pin is display channel 3 source clock, VP_CLKIN3
TS1_CLKO
DVDD33
(I).
-
VP_CLKO2
AA9
O/Z
VPIF display channel 2 output clock (O/Z).
DVDD33
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2)
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3)
Specifies the operating I/O supply voltage for each signal
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Device Overview
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