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TMS320DM6467 Datasheet(PDF) 16 Page - Texas Instruments |
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TMS320DM6467 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 334 page  www.ti.com 2.4.2 DSP Memory Mapping TMS320DM6467 Digital Media System-on-Chip SPRS403 – DECEMBER 2007 The DSP memory map is shown in Section 2.5, Memory Map Summary. Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections. 2.4.2.1 ARM Internal Memories The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only). 2.4.2.2 External Memories The DSP has access to the following External memories: • DDR2 Synchronous DRAM • Asynchronous EMIF / NOR Flash • ATA 2.4.2.3 DSP Internal Memories The DSP has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM 2.4.2.4 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P) consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The Level 1 Data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB RAM memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device. Table 2-2. C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register 0x0184 0048 - 0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register Device Overview 16 Submit Documentation Feedback |
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