TMP1941AF datasheet(58/354 Pages) TOSHIBA

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TMP1941AF

2003-03-27

TMP1941AF-18

Example: Enabling the INT0 interrupt

IMCGA0.EMCG[01:00] = 10

CG block

IMCGA0.INT0EN = 1

(Set the INT0 sensitivity to the falling edge)

IMC0L.EIM[11:10] = 01

INTC block

IMC0L.IL[12:10] = 101

(Set the interrupt sensitivity to the high level, and the interrupt

priority level to 5.)

All interrupt sources other than those used for STOP/SLEEP wake-up signaling are controlled by the

INTC block.

5.2.4

Interrupt Request Clear Register

765

43210

EICRCG

Name





ICRCG2

ICRCG1

ICRCG0

(0xFFFF_EE20)

Read/Write





Reset Value





Function

Clear interrupt request

000: INT0

100: INT4

001: INT1

101: Reserved

010: INT2

110: Reserved

011: INT3

111: INTRTC

Note 1:

Clearing the INT0-INT4 and INTRTC interrupt requests, if programmed for STOP/SLEEP wake-

up signaling, requires two register settings: first, the EICRCG register in the CG block, and

then the INTCLR register in the INTC block. The clearing of other interrupt sources is

controlled through the INTCLR register alone.

Note 2:

In cases where INT0-INT4 are not used for STOP/SLEEP wake-up signaling, they are controlled

by the INTC block in the same way as other interrupt sources. INTRTC is controlled by both

the CG and INTC blocks, regardless of whether it is used for wake-up signaling.

TMP1941AF Datasheet(PDF) 58 Page - Toshiba Semiconductor

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