All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

No internal reset generator or gated clock

Scan test ready

Technology independent HDL source code

Core can be fully customized

1 GHz virtual clock frequency compared to

original implementation

DESIGN FEATURES

SYNCHRONIZED BEFORE INTERNAL USE

The DF6805 can address up to 64K

bytes of Data Memory. The lowest 64

Bytes is reserved for Special Function Reg-

isters area. Data Memory can be imple-

mented as synchronous or asynchronous

RAM

Up to 64 System Function Regis-

ters(SFRs) may be implemented in the

DF6805 design.

Up to 64kB of Program Memory may be

implemented to the DF6805 design. Pro-

gram Memory can be implemented as syn-

WITHOUT ANY MICROCODE

.

PERIPHERALS

The peripherals listed below are implemented

in standard configuration of DF6805.

Processor execution control

Read, write all processor contents

Hardware execution breakpoints

Three wire communication interface

Four 8-bit I/O Ports

Interrupt Controller

7 interrupt sources

7 priority levels

Dedicated Interrupt vector for each interrupt

source

Main16-bit timer/counter system

16 bit free running counter

Timer clocked by internal source

16-bit Compare/Capture Unit

Two independent input-capture functions

Two output-compare channels

Events capturing

Pulses generation

Digital signals generation

Gated timers

Sophisticated comparator

Pulse width modulation

Pulse width measuring

Full-duplex UART - SCI

Standard Nonreturn to Zero format (NRZ)

8 or 9 bit data transfer

Integrated baud rate generator

Noise, Overrun and Framing error detection

IDLE and BREAK characters generation

Wake-up block to recognize UART wake-up

from IDLE condition

Three SCI related interrupts

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

Phone & email support