All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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SCI

- The SCI is a full-duplex UART type

asynchronous system, using standard non

return to zero (NRZ) format : 1 start bit, 8 or 9

data bits and a 1 stop bit. The DF6805 resyn-

chronizes the receiver bit clock on all one to

zero transitions in the bit stream. Therefore

differences in baud rate between the sending

device and the SCI are not as likely to cause

reception errors. Three logic samples are

taken near the middle of data bit time, and

majority logic decides the sense for the bit.

For the start and stop bits seven logic sam-

ples are taken. Even if noise causes one of

these samples to be incorrect, the bit will still

be received correctly. The receiver also has

the ability to enter a temporary standby mode

(called receiver wakeup) to ignore messages

intended for a different receiver. Logic auto-

matically wakes up the receiver in time to see

the first character of the next message. This

wakeup feature greatly reduces CPU over-

head in multi-drop SCI networks. The SCI

transmitter can produce queued characters of

idle (whole characters of all logic 1) and break

(whole characters of all logic 0). In addition to

the usual transmit data register empty (TDRE)

status flag, this SCI also provides a transmit

complete (TC) indication that can be used in

applications with a modem.

DoCD

ware debugger provides debugging capability

of a whole SoC system. In contrast to other

on-chip debuggers DoCD™ provides non-

intrusive debugging of running application. It

can halt, run, step into or skip an instruction,

read/write any contents of microcontroller in-

cluding all registers, internal, external, pro-

gram memories, all SFRs including user de-

fined peripherals. Hardware breakpoints can

be set and controlled on program memory,

internal and external data memories, as well

as on SFRs. Hardware breakpoint is executed

if any write/read occurred at particular address

with certain data pattern or without pattern.

face and complete set of tools to communi-

cate and work with core in real time debug-

ging. It is built as scalable unit and some fea-

tures can be turned off to save silicon and

reduce power consumption. A special care on

power consumption has been taken, and

when debugger is not used it is automatically

switched in power save mode. Finally whole

debugger is turned off when debug option is

no longer used.

OPTIONAL

PERIPHERALS

There are also available an optional pe-

ripherals, not included in presented DF6805

Microcontroller Core. The optional peripherals,

can be implemented in microcontroller core

upon customer request.

SPI – Master and Slave Serial Peripheral

Interface

Supports speeds up ¼ of system clock

Mode fault error

Write collision error

Software selectable polarity and phase of se-

rial clock SCK

System errors detection

Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

Interrupt generation

I2C bus controller - Master

7-bit and 10-bit addressing modes

NORMAL, FAST, HIGH speeds

Multi-master systems supported

Clock arbitration and synchronization

User defined timings on I2C lines

Wide range of system clock frequencies

Interrupt generation

I2C bus controller - Slave

NORMAL speed 100 kbs

FAST speed 400 kbs

HIGH speed 3400 kbs

Wide range of system clock frequencies

User defined data setup time on I2C lines

Interrupt generation

PWM – Pulse Width Modulation Timer

Fixed-Point arithmetic coprocessor

Floating-Point

arithmetic

coprocessor

IEEE-754 standard single precision

Floating-Point math coprocessor - IEEE-

754 standard single precision real, word

and short integers