All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device

Speed

grade

Logic Cells

CYCLONE

-6

1689

79 MHz

STRATIX

-5

1690

83 MHz

MERCURY

-5

1671

85 MHz

APEX II

-7

1850

63 MHz

APEX20KC

-7

1698

55 MHz

APEX20KE

-1

1698

47 MHz

ACEX1K

-1

1739

41 MHz

FLEX10KE

-1

1739

41 MHz

Core performance in ALTERA® devices

Area utilized by the each unit of DF6805 core

in vendor specific technologies is summarized

in table below.

Component

Area

[LC]

[FFs]

CPU*

1134

153

Main Timer

110

55

COM/CAP

150

60

Watchdog

29

14

UART - SCI

272

124

I/O Ports

161

64

Total area

1856

470

*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus

Controller with support for 64KB RAM, External IRQ pin Interrupt Con-

troller

Core components area utilization

IMPROVEMENT

For user the most important is application

speed improvement. The most commonly

used arithmetic functions and theirs improve-

ment are shown in table below. Improvement

was computed as {M68HC04 clock periods}

divided by {DF6805 clock periods} required to

execute an identical function. More details are

available in core documentation

Function

Improve-

ment

8-bit addition (immediate data)

4

8-bit addition (direct addressing)

4

8-bit addition (indirect addressing)

3,6

8-bit subtraction (immediate data)

4

8-bit subtraction (direct addressing)

4

8-bit subtraction (indirect addressing)

3,6

16-bit addition (immediate data)

4

16-bit addition (direct addressing)

4

16-bit addition (indirect addressing

3,6

16-bit subtraction (immediate data)

4

16-bit subtraction (direct addressing)

4

16-bit subtraction (indirect addressing

3,6

Multiplication

5

Division

5

DF68XX FAM I LY O V ERVI EW

The main features of each DF68XX family member have been summarized in table below. It gives

a briefly member characterization helping user to select the most suitable IP Core for its application.

User can specify its own peripheral set (including listed below and the others) and requests the core

modifications.

Design

DF6805

64k

64k

-

7

7

-

-

*

2/2*

1*

*

4

+

*

-

6 700

DF6808

64k

64k

-

7

7

-

-

*

22*

1*

*

4

*

-

8 900

DF6811

64k

16M

-

20

17

1*

*

5/3*

1*

*

4

*

*

*

12 000

DF6811CPU

64k

16M

-

3

3

+

1*

*

+

+

+

+

+

+

+

6 500

DF68XX family of High Performance Microcontroller Cores

+ optional

* configurable