All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implemen-

tation. It also permits FPGA prototyping be-

fore ASIC production.

Unlimited Designs

license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

●

○

○

●

○

○

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

SYMBOL

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

Input

Global system clock

rst

Input

Global system reset

cs

Input

Chip select for read/write

datai[31:0]

1

Input

Data bus input

addr[4:2]

2

Input

Register address to read/write

we

Input

Data write enable

datao[31:0]

1

Output Data bus output

irq

Output Interrupt request indicator

1 – data bus can be configured as 8-, 16- or 32- bit

depends on processor’s bus size

2 – address bus is aligned to work with 8- (3:0), 16-

(3:1) or 32- (4:2) bit processors

BLOCK DIAGRAM

Mantissa –

performs operations on mantissa

part of number. The addition, subtraction,

multiplication, division, square root, compari-

son and conversion operations are executed

in this module. It contains mantissas and

work registers.

Exponent –

performs operations on expo-

nent part of number. The addition, subtrac-

tion, shifting, comparison and conversion

operations are executed in this module. It

contains exponents and work registers.

Align –

performs the numbers analyze

against IEEE-754 standard compliance. In-

formation about the data classes are passed

as result to appropriate internal module.

Shifter –

performs mantissa shifting during

normalization, denormalization operations.

irq

we

rst

clk

cs

Mantissa

Align

Shifter

Exponent

Control

Unit

clk

rst

irq

we

cs

Interface