TMP86FS23UG datasheet(189/252 Pages) TOSHIBA

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Page 177

TMP86FS23UG

17. Multiply-Accumulate (MAC) Unit

The TMP86FS23UG includes a multiply-accumulate (MAC) unit.

The MAC unit is capable of executing 16-bit × 16-bit multiplications and 16-bit × 16-bit + 32-bit multiply-accumu-

late operations.

The MAC unit supports only integer arithmetic, not fixed-point or floating-point arithmetic. Both signed and

unsigned operations can be performed.

The MAC unit can only be used in NORMAL1 or NORMAL2 mode. All the registers of the MAC unit are initial-

ized upon entering a mode other than NORMAL mode.

With development tools, if break mode is entered while the MAC unit is calculating, the calculation is continued

but its result is unpredictable. In this case, the calculation must be re-executed after break mode is exited. Do not

write to the multiplicand register in break mode. When the calculation is completed, it is possible to enter break

mode and read the calculation result in break mode.

17.1 Configuration

Figure 17-1 MAC Unit

17.2 Registers

The MAC unit consists of the following registers:

17.2.1 Command Register

The command register is used to enable and disable the MAC unit, specify the arithmetic mode, and clear the

result register.

Table 17-1 Registers in the MAC Unit

Address

Number of Bits

Command register (MACCR)

0FA4H

8 bits

Status register (MACSR)

0FA5H

8 bits

Multiplier data register (MPLDRH, MPLDRL)

0FA7H, 0FA6H

16 bits

Multiplicand data register (MPCDRH, MPCDRL)

0FA9H, 0FA8H

16 bits

Result register (RCALDR4 to RCALDR1)

0FAAH to 0FADH

32 bits

Addend register (MADDR4 to MADDR1)

0FAAH to 0FADH

32 bits

Control circuit

Status

Command

Arithmetic unit

Temporary register 2

Temporary register 3

Result register

Multiplier register

Multiplicand register

Temporary register 1

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