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TMP86FS23UG Datasheet(PDF) 191 Page - Toshiba Semiconductor |
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TMP86FS23UG Datasheet(HTML) 191 Page - Toshiba Semiconductor |
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191 / 252 page ![]() Page 179 TMP86FS23UG Note 1: The status register is initialized when the result register is cleared (RCLR = “1”). Note 2: CARF, ZERF, SIGN, and OVRF are programmed at the end of calculation. They are not affected by a read from the status register. Note 3: ZERF and SIGN are not affected by a write to the addend register. Note 4: In multiply mode, OVRF and CARF are always read as “0”. Note 5: Bit 7 to 5 are always read as “1”. Note: In signed arithmetic mode, bit 15 is treated as the sign bit. Note 1: In signed arithmetic mode, bit 15 is treated as the sign bit. Note 2: Calculation can only be started by writing to both the lower byte (MPCDRL) and upper byte (MPCDRH) of the mul- tiplicand register in this order. Note 3: The multiplicand register can only be programmed when data is written in the order of lower byte and upper byte. If data is only written to the upper byte, the written data cannot be read out. (If data is only written to the lower byte, the written data can be read out.) Note: In signed arithmetic mode, bit 31 contains the sign of the calculation result. CARF Carry flag 0: No carry occurred in multiply-accumulate operation. 1: Carry occurred in multiply-accumulate operation. Read only ZERF Zero flag 0: Calculation resulst is other than “00000000H”. 1: Calculation result is “00000000H”. SIGN Sign flag 0: Result register contents are positive or “00000000H”. 1: Result register contents are negative. OVRF Overflow flag 0: Overflow occurred. 1: No overflow occurred. CALC Operation status flag 0: Calculation not in progress 1: Calculation in progress Multiplier data Register MPLDRH, MPLDRL (0FA7H, 0FA6H) 15 14 13 12 11 10 9876543210 MPLDRH (0FA7H) MPLDRL (0FA6H) (Initial value: 0000 0000 0000 0000) R/W Multiplicand data Register MPCDRH, MPCDRL (0FA9H, 0FA8H) 15 14 13 12 11 10 9876543210 MPCDRH (0FA9H) MPCDRL (0FA8H) (Initial value: 0000 0000 0000 0000) R/W Result Register RCALDR4, RCALDR3 (0FADH, 0FACH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RCALDR4 (0FADH) RCALDR3 (0FACH) (Initial value: 0000 0000 0000 0000) Read only RCALDR2, RCALDR1 (0FABH, 0FAAH) 15 14 13 12 11 10 9876543210 RCALDR2 (0FABH) RCALDR1 (0FAAH) (Initial value: 0000 0000 0000 0000) Read only Addend Register MADDR4, MADDR3 (0FADH, 0FACH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MADDR4 (0FADH) MADDR3 (0FACH) (Initial value: 0000 0000 0000 0000) Write only MADDR2, MADDR1 (0FABH, 0FAAH) 15 14 13 12 11 10 9876543210 MADDR2 (0FABH) MADDR1 (0FAAH) (Initial value: 0000 0000 0000 0000) Write only |
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