TC9WMB1AFK/FU,TC9WMB2AFK/FU

2007-10-19

6

(3)

Acknowledge polling

Acknowledge polling is a feature for determining whether rewrite operation is in progress. During

rewrite operation, generate a start condition followed by a device address, and

W

R/

(

= 0 or 1). The

acknowledge feature does not generate an acknowledge signal while rewrite operation is in progress.

A low acknowledge signal is generated if rewriting has already completed.

If the next instruction is a write, supply a word address and write data subsequently. If the next

instruction is a read, supply a stop condition and then start read operation.

(4)

Write protection

When “high” is received to the write protection (WP) pin, the TC9WMB1A to protect the entire

memory area from being written and the TC9WMB2A to protect the bottom half (80h to FFh) of the

memory area from being written. Rewriting is allowed when “low” is received to the write protection

pin. While a write is in progress, driving the WP pin high does not stop write operation.

Reading is always enabled regardless of whether the WP pin is “high” or “low”

6. Read Operation

Read operation is performed in one of three modes: current address read, random read, and sequential

read.

For reading, a device receives a device address and

W

R/

(

= 1) after a start condition. After read data is

sent, terminate a read operation by generating a high acknowledge signal (or releasing the bus without

supplying an acknowledge signal) and then supplying a stop condition.

(1)

Current address read

The internal address counter maintains the address that is next to the last accessed (read or

written) word address (n). In current address read mode, data is read from address n

+ 1, as indicated

by the address counter.

In current address read mode, supplying a device address and

W

R/

(

= 1) after a start condition,

causes the device to generate a low acknowledge signal and send a data at the address indicated by

the internal address counter.

The address counter is incremented on the falling edge of the SCL pulse where a data at the eighth

bit is sent. If the previous operation was reading data from the last address, the current address is

rolled over to address 0. If the previous operation was writing data to the last address of the page, the

address is rolled over to the first address of the page.

The current address is maintained in an internal register so that it is lost when the power is turned

off. For the first read after power-up, specify an address by performing a random read.

Figure 7

SDA LINE

1 0 1 0

1

D

6

D

4

D

5

D

3

D

1

D

2

D

0

S

T

A

R

T

M

S

B

DEVICE

ADDRESS

R

E

A

D

L

S

B

A

C

K

R

/

W

D

7

READ

DATA

S

T

O

P

N

O

A

C

K

Address

increment

A

1

A

2

A

0