LT1990-10

6

Rev 0

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

∆G

Gain Error

VOUT = ±10V

l

0.95

%

GNL

Gain Nonlinearity

VOUT = ±10V

l

0.03

%

∆G/∆T

Gain vs Temperature

(Note 9)

l

7

20

ppm/°C

VCM

Input Voltage Range

Guaranteed by CMRR

l

-250

250

V

CMRR

Common Mode Rejection Ratio, RTI

VCM = –250V to 250V

l

58

dB

VOS

Offset Voltage, RTI

l

6.7

mV

∆VOS/∆T Input Offset Voltage Drift, RTI

(Note 9)

l

5

22

µV/°C

VOSH

Input Offset Voltage Hysteresis, RTI

(Note 10)

l

250

µV

PSRR

Power Supply Rejection Ratio, RTI

VS = ±1.35V to ±18V, VCM = VREF = 1.25V

l

78

dB

Minimum Supply Voltage

Guaranteed by PSRR

l

±1.35

V

IS

Supply Current

l

375

µA

VOUT

Output Voltage Swing

l

±14.3

V

ISC

Output Short-Circuit Current

Short to V-

Short to V+

l

l

3

10

mA

mA

SR

Slew Rate

VOUT = ±10V, No RL

l

0.4

V/µs

The l denotes the specifications which apply over the temperature range of

-40°C ≤ TA ≤ 85°C. VS = ±15V, RL = 10kΩ, VCM = VREF = 0V, unless otherwise noted. (Note 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: ESD (Electrostatic Discharge) sensitive device. Extensive use of

ESD protection devices are used internal to the LT1990-10, however, high

electrostatic discharge can damage or degrade the device. Use proper ESD

handling precautions.

Note 3: A heat sink may be required to keep the junction temperature

below absolute maximum.

Note 4: The LT1990I-10 is designed, characterized and expected to be

functional over the operating temperature range of –55°C to 125°C, but is

not tested or QA sampled at these temperatures.

Note 5: The LT1990I-10 is guaranteed to meet specified performance from

–40°C to 85°C.

Note 6: Limits are guaranteed by correlation to –5V to 80V CMRR tests.

Note 7: VS = 3V limits are guaranteed by correlation to VS = 5V and

VS = ±15V tests.

Note 8: VS = 5V limits are guaranteed by correlation to VS = 3V and

VS = ±15V tests.

Note 9: This parameter is not 100% tested.

Note 10: Hysteresis in offset voltage is created by package stress that

differs depending on whether the IC was previously at a higher or lower

temperature. Offset voltage hysteresis is always measured at 25°C, but the

IC is cycled to 85°C or –40°C before successive measurement.